Bus Arbitration Research Articles

FASTBUS for Data Acquisition and Control

FASTBUS is a standardized modular data-bus system for data acquisition, data processing and control applications. It is the result of an interlaboratory development undertaken to meet the needs of the high energy physics community. However, the versatility, speed and addressing capability of FASTBUS make it attractive for many other types of application. A FASTBUS system consists of bus Segments which operate independently but dynamically link together as needed for operation passing. This parallel processing feature accounts to a great extent for the high throughput of FASTBUS in multisegment systems. Master modules compete for single or multiple Segment Control through a bus arbitration scheme using assigned priorities. Logical, geographical, secondary and broadcast addressing methods are used to access either data space or control and status register space. Features include block transfers, a sparse data scan and interrupts.

An overview of the proposed american national standard for local distributed data interfaces

The Local Distributed Data Interface (LDDI) Project of X3 Technical Committee X3T9 has resulted in three draft proposed American National Standards for a high performance local area network. The proposed standards are organized in accordance with the ISO Reference Model for Open Systems Interconnection and encompass the lowest two protocol layers (data link and physical) of the model, plus a serial broadband coaxial bus interface. The intended application of the LDDI is as a backend network for the interconnection of high performance CPUs and block transfer peripherals such as magnetic disk and tapes. A carrier-sense multiple access with collision prevention (CSMA-CP) distributed bus arbitration protocol is employed. The cable interface supports the attachment of up to 28 ports over a cable distance of 0.5 km (8 ports may be attached to a 1 km cable) at a transfer rate of 50 Mbit/s.

Use of microprocessors to control a photographic plate measuring machine

GALAXY is an automatic high-speed photographic plate measuring machine. It is used for measuring the positions of star images on astronomical photographs. Installed in 1972, GALAXY is operated by the Royal Greenwich Observatory as a national facility, for the Science and Engineering Research Council. In recent years the machine has become unreliable and it was decided to rebuild its electronic control system. The measuring machine is controlled by three MC68000 microcomputers operating in parallel. One is responsible for receiving commands from the operator, supplying status information and directing the operation of the machine. Another is dedicated to the high-speed analysis of image pixel data to produce approximate image positions in ‘Search’ mode. The third controls the operation of the machine and prepares data for the image processor. The three microcomputers are interfaced to a common GALAXY bus under the control of a bus arbitration card; this allows controlled access to the GALAXY bus by each processor.

Interconnection Hardware for Distributed-Systems Communications Architecture

Interconnection hardware strategies are overviewed in light of loosely-coupled computing systems. Bus issues, arbitration and communication principles are outlined with a direction towards future bus definition and standards. High bandwidth interconnection schemes using multi-port memory controllers and cross-point switches are presented followed by a specific design of a cross-point inter-connection switch. Future research in distributed computing is discussed, providing a comprehensive set of architectural and software issues.

A fully-distributed arbiter for multiprocessor systems

Abstract In this paper the problem of shared resources access management in multiprocessor system is examined. After a brief summary of existing techniques, the architectural and implementation details of a bus arbiter are presented. In the proposed solution, concurrent resource requests are stored in parallel by means of a memorization logic; the arbitration function is then performed by a set of daisy chained modules which honour each request following a rotating priority scheme. Following features are met in the proposed arbiter: (1) high modularity in all arbitration sections; (2) high arbitration speed; (3) indivisible memory-reference facility; and (4) stuck-at-one failures fault-tolerance in the memorization logic.

High-speed bus arbiter for multiprocessors

Shared-bus interconnection schemes normally suffer from insufficient capacity. Increasing their bandwidth reduces the problem but makes bus arbitration somewhat difficult. This paper presents a fair bus-arbiter design, its implementation and simulation results. Although the techniques originated from the particular constraints of the architecture considered, it is generally applicable to high-speed arbitration problems and has a low hardware cost.

A fully distributed arbiter for multiprocessor systems

In this paper the problem of shared resources access management in multiprocessor system is examined. After a brief summary of existing techniques, the architectural and implementation details of a bus arbiter are presented. In the proposed solution, concurrent resource requests are stored in parallel by means of a memorization logic; the arbitration function is then performed by a set of daisy chained modules which honour each request following a rotating priority scheme. Following features are met in the proposed arbiter: (1) high modularity in all arbitration sections; (2) high arbitration speed; (3) indivisible memory-reference facility; and (4) stuck-at-one failures fault-tolerance in the memorization logic.

Eurobus—the UK-designed general-purpose backplane bus

Eurobus was designed by the UK Ministry of Defence and Ferranti Computer Systems Ltd. Independence from any particular family of control processors is achieved by using a dedicated bus arbiter. Interrupt and data transfer on Eurobus are described with details of the handshaking sequence and protocol. The electrical characteristics qualified as Eurobus B are described. A physical description for Eurobus 18A (18 address; 16 data bit) concludes the paper.

A multiple microprocessor system for biomedical signal processing

This paper presents a detailed description of the organization and design of a multiple-microprocessor computer based on TMS9900 microprocessors. The machine is organized around a shared bus with each processor having access to local memory. Details are given of the addressing structure used, the shared bus arbitration scheme and associated logic and the facilities for processor synchronization. The shared memory/local memory partition is defined at the processor level. Arbitration is based on circular polling of shared memory requests. Processor synchronization is effected by a hardware implemented test and set busy flag memory cycle. A low-level operating system for the multiple microprocessor computer is discussed. Application of this system to the real-time analysis of electromyograms (EMG) is explored. It is concluded that this system demonstrates the simplicity of a small-scale multiple-microprocessor computer, its applicability and potential ease of application to biomedical signal processing problems.

FASTBUS Slaves -- A Designers View

Although FASTBUS has features built into it which allow complex interconnections and multiple Masters, the rules for implementing Slaves are very simple. The first time designer of Slave Modules should not be intimidated by the 200 pages of the FASTBUS document. About 90% of the specification is associated with system implications that do not impact Slave design. This paper will review the basic logic and timing requirements for FASTBUS Slave design. Also, some examples of implementation will be shown. The discussion which follows assumes that mastership of the bus has been gained. Bus arbitration, system interconnection, message routing, etc. are separate topics and will not be discussed here. These topics affect only the design of devices which operate at the system level since FASTBUS Slave modules have been specified to be completely transparent to these system considerations.

Serial data bus control method

The explosion of Distributed Processing Systems in recent years has created requirements for interconnecting large numbers of diverse processing elements. The Performance characteristics of these processors span virtually the entire spectrum of speed and capability from small minicomputers to large-scale, general-purpose, multiprocessor systems. Implicit, therefore, in the communications interconnection are features such as high-speed, high-survivability, fault tolerance, and expandability. Sperry Univac has developed a Serial Data Bus as part of a contract with the Canadian government. Many of the system design problems which were addressed during the development period required unique solutions; the principal issues being Bus Access Time and Casualty Recogfiguration. The Bus Access Time issue eventually evolved into a design problem which demanded a highly sophisticated and efficient Bus Arbitration Mechanism. This paper provides the background and detailed technical descriptions of the actual designs which were chosen for these two key areas.

FASTBUS - Details of Addressing and Bus Mastership

FASTBUS is a new high-speed data-acquisition standard under development by the Physics Community. A general overview of FASTBUS can be found in Reference 1. This paper will deal with two specific areas: addressing and bus arbitration. These two topics are unique to FASTBUS and will require some reorientation of the users relative to their CAMAC experiences.

Improvements of the multiprocessing capabilities of microprocessor busses

This paper deals with an electrically short type independent microprocessor bus that is capable of handling multiprocessor tasks. It features three different and compatbile bus arbitration mechanisms and a periodical parallel poll on the data lines to recognize interrupt requests. A bus clock defines the exact timing of the transfer operations which are organized on a handshake basis. Three sub-busses, the Coded System bus, the Operation Mode bus and the coded Function bus serve to manage system status, system operation level and data handling operations.

The minerva multi-microprocessor

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.