FASTBUS Slaves -- A Designers View

Abstract

Although FASTBUS has features built into it which allow complex interconnections and multiple Masters, the rules for implementing Slaves are very simple. The first time designer of Slave Modules should not be intimidated by the 200 pages of the FASTBUS document. About 90% of the specification is associated with system implications that do not impact Slave design. This paper will review the basic logic and timing requirements for FASTBUS Slave design. Also, some examples of implementation will be shown. The discussion which follows assumes that mastership of the bus has been gained. Bus arbitration, system interconnection, message routing, etc. are separate topics and will not be discussed here. These topics affect only the design of devices which operate at the system level since FASTBUS Slave modules have been specified to be completely transparent to these system considerations.