Buried Channel CCD Research Articles

Improving charge transfer efficiency in CCDs: A SILVACO-based numerical study

In this study, we investigate the charge transfer efficiency (CTE) of a radiation-damaged charge-coupled device (CCD) subjected to proton radiation levels typical of space-borne experiments, nuclear imaging, and particle detection. The primary factor affecting CTE in such damaged CCDs is the trapping of charge carriers by bulk states. Our analysis examines CTE as a function of temperature, and radiation-created traps (trap levels). We employed a two-dimensional numerical model using the SILVACO semiconductor simulation software to simulate the dynamic transfer process in a buried-channel CCD (BCCD) with a three-phase clock pulse driver. After setting the appropriate physical models and the suggested deep traps levels in the channel region. The simulations demonstrate that the CTE shows a nonlinear dependence on temperature, with a charge transfer inefficiency (CTI) peaking at 7x10-6 at 135 K and reaching a minimum value of 2x10-6 around 200 K. These simulated results closely match the experimental data found in the literature, providing a comprehensive understanding of the impact of radiation-induced traps on the dynamic charge transfer processes in CCDs.

Design and optimization of BCCD in CMOS technology

This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency (CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.

Analysis and simulation of entirely saturated unilateral laser spot tails in BCCD.

A new phenomenon involving the entire saturation of unilateral tails of buried channel charge-coupled devices (BCCDs) under laser radiation is observed in this study. A physical model related to this phenomenon is constructed based on the assumption that the charge transfer inefficiency of BCCD is a jump function of signal charge quantity. The profile of a spot tail under laser radiation is simulated using this self-developed model. The simulation results are compared with experimental findings to validate this model.

Effects of proton and neutron irradiation on dark signal of CCD

The proton and neutron irradiation and annealing experiments are carried out on a domestic buried channel CCD (charge-coupled devices), Monte Carlo method being applied to calculate the energy deposition of scientific CCD irradiated by proton and neutron, and the radiation damage mechanism of the device is analyzed. The displacement damage dose in N+ buried channel is simulated. During irradiation and annealing experiments, the main parameter (dark signal) is investigated. Results show that the dark signal of the buried channel CCD irradiated by 10 MeV proton and 1 MeV neutron rises obviously. With the same fluence, the increase of dark signal and the displacement damage dose in N+ buried channel caused by 10 MeV proton is larger than that by 1 MeV neutron. Dark signal caused by proton irradiation is divided into surface dark signal and bulk dark signal. Oxide-trapped-charges and interface states may be caused by ionization-generated surface dark signal, and the bulk defects may be caused by displacement-generated bulk dark signal. Neutron irradiation only affects the bulk dark signal. Defects and their annealing temperature are studied. The dark signal of CCD irradiated by proton is greatly reduced after annealing, this phenomenon means that the dark signal is mainly affected by ionization. The proportion of bulk dark signals in total dark signals can be calculated by the remainder of dark signal after annealing, and it is at most about 20% or less. From the formula, the position of energy level of bulk defects has an obvious influence on the bulk dark signal. The energy level in the middle of the forbidden band can provide effective hot carriers. Combining the results of experiment and simulation, when the displacement damage doses in N+ buried channel are the same, the bulk dark signal produced by proton is nearly the same as that produced by neutron. This phenomenon means that the defect levels in the forbidden band gap caused by proton and neutron irradiation have the same contributions to dark signal generation. Effect of proton and neutron irradiation on the bulk dark signal is homogeneous. The displacement damage dose can be used to characterize the degradation degree of the bulk dark signal in CCD after irradiation.

Study of CCD Transport on CMOS Imaging Technology: Comparison Between SCCD and BCCD, and Ramp Effect on the CTI

This paper presents measurements performed on charge-coupled device (CCD) structures manufactured on a deep micrometer CMOS imaging technology, in surface channel CCD and in buried channel CCD mode. The charge transfer inefficiency is evaluated for both CCD modes with regard to the injected charge, and the influence of the rising and falling time effect is explored. Controlling the ramp and especially reducing its abruptness allows to get much lower charge transfer inefficiency in buried CCD mode. On the contrary, we did not observe any effect of the ramp on surface channel CCD mode because of the presence of interface traps at the silicon-oxide interface.

Performance of Deep-Depletion Buried-Channel $n$-MOSFETs for CMOS Image Sensors

Buried-channel (BC) MOSFETs are known to have better noise performance than their surface-channel (SC) counterparts when used as a source follower in modern charge-coupled devices (CCDs). CMOS image sensors are finding increasing applications and compete with CCDs in high-performance imaging, but BC transistors are rarely used in CMOS. As a part of the development of charge storage using CCDs in CMOS, we designed and manufactured deep-depletion BC n-type MOSFETs in 0.18- μm CMOS image sensor process. The BC transistors are designed in a way similar to the source followers in a typical BC CCD, and feature deep n-channel implant and threshold voltage exceeding -2.5 V. In this paper, we report the results from their characterization and compare them with normal enhancement mode and “zero-threshold” SC devices. In addition to the detailed current-voltage and noise measurements, 2-D semiconductor device simulation results are presented to illustrate and understand the different conditions affecting the channel conduction and the noise performance of the BC transistors. We show that under optimal bias conditions the noise performance of the BC transistors can be superior despite their lower gain as in-pixel source followers.

3-Dimensional Numerical Analysis of Deep Depletion Buried Channel MOSFETs and CCDs

The visual analysis of buried channel (BC) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of EVEREST for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately 4-5% error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

Determination of the Depletion Depth of the Deep Depletion Charge-Coupled Devices

A 3-D numerical simulation of a buried-channel CCD (Charge Coupled Device) with a deep depletion has been performed to investigate its electrical and physical behaviors. Results are presented for a deep depletion CCD (EEV CCD12; JET-X CCD) fabricated on a high-resistivity <TEX>$(1.5k\Omega-cm)\;65{\mu}m$</TEX> thick epi-layer, on a <TEX>$550{\mu}m$</TEX> thick p+ substrate, which is optimized for X-ray detection. Accurate predictions of the Potential minimum and barrier height of a CCD Pixel as a function of mobile electrons are found to give good charge transfer. The depletion depth approximation as a function of gate and substrate bias voltage provided average errors of less than 6%, compared with the results estimated from X-ray detection efficiency measurements. The result obtained from the transient simulation of signal charge movement is also presented based on 3-Dimensional analysis.

MCT heteroepitaxial 4 × 288 FPA

4 × 288 heteroepitaxial mercury–cadmium telluride (MCT) linear arrays for long wavelength infrared (LWIR) applications with 28 × 25 micron diodes and charge coupled devices (CCD) silicon readouts were designed, manufactured and tested. MCT heteroepitaxial layers were grown by MBE technology on (0 1 3) GaAs substrates with CdZnTe buffer layers and had cutoff wavelength λ co≈11.8±0.15 μm at T=78 K. To decrease the surface influence of carrier recombination processes the compositionally dependent layers with increase of Cd content both toward the surface and HgCdTe/CdZnTe boundary interface were grown. Silicon readouts with CCD multiplexers with input direct injection circuits were designed, manufactured and tested. The testing procedure, to qualify readout integrated circuits on wafer level at T=300 K, was worked out. The silicon readouts for 4 × 288 arrays, with skimming and partitioning functions included were manufactured by n-channel MOS technology with buried or surface channel CCD register. The HgCdTe arrays and Si CCD readouts were hybridized by cold welding indium bumps technology. With skimming mode used for 4 × 288 MCT n–p-junctions, the detectivity for several tested 4 × 288 arrays was within D λ ∗≅9×10 10–1.8×10 11 cm Hz 1/2/W for background temperature T b=295 K.

The physics of the low-energy tail in the ACIS CCD: The spectral redistribution function

We studied the response of high-resistivity MOS CCDs to monochromatic X-ray illumination at energies ranging from 1.47 to 5.9 keV and discovered a new feature in the low-energy tail of the response function. We attribute it to the photons interacting in the gate insulator and explain the shape of the entire low-energy tail assuming that it is formed by electron charge clouds partially formed in the gate oxide. The size of the charge clouds derived from this model is much smaller than previously reported. This can be explained by a different field distribution in a buried channel CCD.

360×360 element three-phase very high frame rate burst image sensor: design, operation and performance

Design, fabrication, operation and performance are described for a 360/spl times/360 element very high frame rate (VHFR) image sensor that can capture images at a frame rate of up to 10/sup 6/ frames/s. This VHFR imager has 50/spl times/50 /spl mu/m macropixels, each consisting of a high-speed zero-lag photodetector with a 13.5% fill factor and 30 stages of serial-parallel type buried-channel CCD registers for storage and readout of the last 30 image frames acquired. Readout of this imager is similar to a frame transfer CCD consisting of four quadrants. Each quadrant contains one million pixels, readout at a relatively slow rate compatible with low readout noise, and PC class microcomputer-based data acquisition and storage. This imager is designed using SiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric, four levels of polysilicon, three levels of metal, eight implants, 21 photo masks using 1.5-/spl mu/m design rules, and it has four output ports. The high-speed photodetector is designed in the form of a graded three-potential-level pinned-buried BCCD structure. This 33-/spl mu/m long photodetector can achieve complete readout of photogenerated electrons in less than 0.1 /spl mu/s.

Experimental demonstration of a buried-channel charge-coupled device in 6H silicon carbide

Fundamental operation of the first buried-channel charge-coupled device (BCCD) in 6H-SiC is presented. The n-type buried-channel was formed by ion implantation of nitrogen, and a double level overlapping-polysilicon-gate process was adapted to the SiC MOS system. An electron mobility of 200 cm/sup 2//Vs was measured in the channel, which is doped 1.6/spl times/10/sup 17/ cm/sup -3/. An eight-stage, four-phase BCCD shift register was operated in the pseudo-two-phase configuration at room temperature. At 5.5 kHz, the charge transfer efficiency is greater than 99.4%.

A 9-b charge-to-digital converter for integrated image sensors

Charge-to-digital conversion offers advantages over conventional charge readout techniques because it performs digitization directly in the charge domain. The approach consolidates hardware, reduces power and weight, and eliminates many sources of noise and nonlinearity. This paper introduces an architecture for a charge-to-digital converter (CDC) that is tailored toward a charge-coupled device (CCD) implementation. New methods of generating charge, sensing charge, and comparing charge packets are described that improve conversion accuracy. Factors limiting device performance are discussed. Measured results are presented for two prototype CDCs. The first, using buried channel CCDs, is optimized for resolution. It achieves 56 dB spurious free dynamic range (SFDR) at a 2 MHz sampling rate and operates from 5 V. The second, using surface channel CCDs, is optimized for power and speed. It achieves 49 dB SFDR at a 15 MHz sampling rate and consumes 13 mW power at its maximum sampling rate of 22 MHz.

High-density and high-quality frame transfer CCD imager with very low smear, low dark current, and very high blue sensitivity

When the channel width of an FET becomes of the same order of magnitude as the depth of the gate depletion region, an increase of the threshold voltage is observed. This narrow channel effect has been applied successfully in creating an asymmetric potential well under an electrode for two-phase CCD operation. The feasibility of this structure has been confirmed in a 242-element analog delay line. The application is now extended to a 800 H/spl times/492 V frame transfer-type buried channel CCD imager with 14.31818 MHz frame shift, which results in a very low smear level of 0.01%, which is good enough for low-cost multimedia video camera applications.

Reduction of fixed loss in buried-channel CCD's operating at 77 K

The authors describe studies on charge transfer loss in buried-channel charge-coupled devices (BCCD's) at 77 K. Experiments suggest that the fixed loss occurs mostly during the last transfer from phase clock to output diffusion. It is shown that this loss can be reduced by reducing the doping concentration in the buried channel and introducing a potential step in the middle of the storage well along the charge-flow direction. Transfer inefficiencies as low as 8.6*10/sup -5/ without fat zero at 3-MHz clock rate are observed at 77 K.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Buried channel charge-coupled device on gas-source MBE grown InP

The first epitaxial-channel InP CCDs on semi-insulating substrates have been demonstrated using gas-source MBE grown layers. Channel isolation was achieved using a mesa etch, and the two level overlapping gate structure was insulated using indirect plasma enhanced CVD grown SiO2. Initial results indicate stale device operation with charge transfer efficiencies, at 1–3MHz operating frequencies, of ∼0.99.

Improved drift in two-phase, long-channel, shallow buried-channel CCDs with longitudinally nonuniform storage-gate implants

Two-phase buried-channel charge-coupled devices (CCDs) with a gradient in the storage wells, generated by a nonuniform channel doping parallel to the surface, were studied at room temperature and at 77 K. The built-in drift fields improve the charge transfer efficiency by more than an order of magnitude, consistently with two-dimensional simulations. >

A buried-channel charge-coupled device with non-overlapping gate structure for a CMOS/BCCD process

A buried-channel CCD is presented, suitable for integration in a high-energy ion-implanted CMOS process. The BCCD channel is high-energy ion-implanted and the gate structure is non-overlapping. The required submicron spacings between adjacent gates are created by a sequence of processing steps. No demands are imposed on the lithography used. SEM photographs show a well-defined gate structure with straight spacings exhibiting minor width variation. The parasitic potential well, associated with the presence of spacing between the gates, has little influence on charge transport performance. Delay lines have been operated with transfer inefficiency of 10-5 and less.

Noise analysis and measurements on buried channel charge coupled devices

Abstract Noise analysis of buried channel CCD by computer simulation is presented. The potential profile and signal charge distribution in potential well are obtained by solving Poisson's equation with a depletion approximation model. According to this model, it is possible to predict the volume occupied by signal charges in potential well. Thereby, the well capacitance and free carrier density are obtained. Then the device noise in the buried channel charge‐coupled device, including the output reset noise, dark current noise, transfer noise and electrical injection noise at the input, can be calculated. Also, the charge handling capacity can be evaluated by integrating over the charge occupied volume. The dependences of the electrical injection noise and transfer noise on charge packet size and operating frequency have been calculated. This model can also calculate quantitatively the dependence of the charge handling capacity and the position of maximum potential on the magnitude of clock voltage. The no...

CCD focal-plane image reorganization processors for lossless image compression

Four image reorganization ICs that enable real-time difference encoding for hierarchical lossless image compression are reported. Two image reorganization processors are realized on the focal-plane and two are designed for hybridization to a separate imager IC. The two focal-plane ICs represent the first integration of a 256*256 buried-channel frame-transfer CCD image sensor with additional charge-domain circuitry to enable image reformatting at video rates (28 frames/s). The four ICs generate pyramidal pixel output in 3*3 blocks with the center pixel first. Pixel data reorganization is performed through simultaneous readout of three rows of data, followed by pixel resequencing and sampling to provide differential output. A novel architecture provides simultaneous readout of multiple imager rows on the focal-plane ICs. The ICs have achieved a charge-transfer efficiency (CTE) of 0.99996 in the conventional horizontal and vertical CCD registers, and a CTE of 0.99994 in the SP/sup 3/ registers. >