Bumping Process Research Articles

Low-cost bump bonding activities at CERN

Conventional bumping processes used in the fabrication of hybrid pixel detectors for High Energy Physics (HEP) experiments use electroplating for Under Bump Metallization (UBM) and solder bump deposition. This process is laborious, involves time consuming photolithography and can only be performed using whole wafers. Electroplating has been found to be expensive when used for the low volumes which are typical of HEP experiments. In the low-cost bump bonding development work, electroless deposition technology of UBM is studied as an alternative to the electroplating process in the bump size / pitch window beginning from 20 μm / 50 μm. Electroless UBM deposition used in combination with solder transfer techniques has the potential to significantly lower the cost of wafer bumping without requiring increased wafer volumes.A test vehicle design of sensor and readout chip, having daisy chains and Kelvin bump structures, was created to characterize the flip chip process with electroless UBM. Two batches of test vehicle wafers were manufactured with different bump pad metallization. Batch #1 had AlSi(1%) metallization, which is similar to the one used on sensor wafers, and Batch #2 had AlSi(2%)Cu(1%) metallization, which is very similar to the one used on readout wafers. Electroless UBMs were deposited on both wafer batches. In addition, electroplated Ni UBM and SnPb solder bumps were grown on the test sensor wafers. Test assemblies were made by flip chip bonding the solder-bumped test sensors against the test readout chips with electroless UBMs. Electrical yields and individual joint resistances were measured from assemblies, and the results were compared to a well known reference technique based on electroplated solder bumps structures on both chips. The electroless UBMs deposited on AlSi(2%)Cu(1%) metallization showed excellent electrical yields and small tolerances in individual joint resistance. The results from the UBMs deposited on AlSi(1%) metallization were non-uniform and closer inspection revealed micro cracks at aluminum — electroless nickel interface. UBM deposition was also done for Timepix wafers and solder ball placement process was prototyped with 40 μm balls.

Measuring Manufacturing Yield for Gold Bumping Processes Under Dynamic Variance Change

Recently, the technology of gold bumping has become more popular due to high demand for LCD driver ICs. The requirement of higher resolution application, however, will increase the difficulties for manufacturing the gold bumps due to their high pin counts. For gold bumping processes, bump height is one of the key parameters to control process yield. In reality, some inevitable process variations and shifts regarding the bump height may occur under dynamic manufacturing environment. Conventionally, manufacturing yield for gold bumping processes is calculated under the assumption that the processes are stable. In practice, however, the processes are dynamic, particularly, in the operation of Au-plating in gold bumping factories. To obtain accurate measure of the manufacturing yield, we present a capability index method for manufacturing yield calculation with dynamic variance change considerations. Using this method, the magnitude of the undetected variance change, which is function of the detection power of the S 2 chart, is incorporated into the adjusted calculation of manufacturing yield. The detection powers of the S 2 chart under various subgroup sizes are tabulated. For illustration purposes, a real application in a gold bumping factory which is located in the Science-based Industrial Park in Hsinchu, Taiwan, is presented.

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

A new bumping process on a Si die by electroplating without a photo-resist-mold (PRM) was assessed for the three dimensional (3D) stacking of Si dice. In this process, solder bumps were deposited selectively onto the surface of a Cu plugged-through silicon-via (TSV) in a Si die. Since lithography related processes to make a PRM for solder bumping were omitted, it can reduce the production time and cost for bumping. The substrate was a Si wafer, and TSVs were produced by deep-ion-reactive-etching (DRIE). As an insulation layer, SiO2 was formed by high-density-plasma-chemical-vapor-deposition (HDPCVD) or wet oxidation method. A Ti adhesion and an Au seed layers were deposited by sputtering. Cu was plugged into the vias by pulsed direct-current (DC) electroplating. The backside of the Si wafer was ground by chemicalmechanical-polishing (CMP). Sn bumps were electroplated on the Cu plugged vias by a current supplied through a Cu-overplated layer (COL) on the vias surface. As experimental results, wet oxidation provided a uniform SiO2 thickness through the via depth, whereas the SiO2 thickness by HDPCVD decreased with the via depth. The Ti and Au thicknesses also decreased along the via depth. In electroplating for Cu plugging,

Local melt process of solder bumping by induction heating reflow

PurposeThe purpose of this paper is to describe a local melt process of solder bumping employed in electronic packaging applications by an induction heating reflow method, for a combined numerical and experimental study involving a temperature measurement using an infrared thermometer during the reflow process and microstructural observations after reflow, which can be used to control the height and shape of solder interconnects.Design/methodology/approachIn the induction heating reflow process, the temperature distribution within the solder ball during the heating phase is of prime importance for the success of the process and the geometry control quality of final joints. This paper investigates the local melt process of solder balls reflowed onto Cu/Ni/Au pads, and focuses on the effect of the inductive heat on the thermal distribution during the melting process. A finite‐element model is applied to simulate the thermal field in a solder bump during the induction heating period in a reflow process. The effects of the coil current and the electromagnetic frequency on the thermal performance are investigated by using the validated thermal model. The local melt phenomenon in the solder joint is observed and identified by the microstructures taken using scanning electron microscopy.FindingsIn this paper, the numerical results match the experimental results quite well to validate the finite element modeling model. The local melt phenomenon predicted by simulation, and verified by experiments, is demonstrated to be capable of controlling the solder joint shape. Several parametric studies are carried out to understand the effects of different frequencies during assembly, and to suggest that a higher frequency is easier to get a greater temperature gradient, thus a more obvious local melt phenomenon, which is good for achieving the geometry control for solder joints.Originality/valueThe findings of this paper will help to understand the detailed solder bumping process during induction heating reflow and the effects of electromagnetic field frequency on solder joint shape controlling.

56.1: A Novel Composite Bump Design for Chip‐On‐Glass Package Using Non‐Conductive Adhesive Film

AbstractA novel composite bump, Smart bump, structure has been successfully developed for chip‐on‐glass (COG) package using non‐conductive adhesive film (NCF). We have successfully verified the low contact resistance and high reliabilities using Smart bump and COG NCF process for the packages of 17 “W, 12.1” and 2.4 “TFT‐LCD modules. We have realized that COG NCF process with Smart bump is simpler and lower cost in consumable materials than the conventional COG ACF process with Au bump. The COG NCF process also allows fine‐pitch‐driver package for high‐resolution TFT‐LCDs, and has a higher process yield in pilot production.

Wafer Bumping Process and Inter-Chip Connections for Ultra-High Data Transfer Rates in Multi-Chip Modules With Superconductor Integrated Circuits

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Josephson junction logic cells and superconductor microstrip lines are able to process and transfer digital data with rates up to several hundred GHz as has been demonstrated in single-chip experiments. However, the existing chip-level bumping technique in InSn solder and resulting inter-chip connections do not allow expanding these rates to multi-chip circuits. We developed a wafer-level bumping technology using lithographically-defined bumps deposited either by e-beam evaporation or electroplating, and proposed and implemented a novel design of high-frequency chip interconnects. Chip-to-chip single-flux-quantum pulse transmission rates reaching 110 GHz have been achieved. The observed rates were limited not by the interconnects but by the speed of on-chip test circuitry fabricated in the framework of 4.5 <formula formulatype="inline"> <tex Notation="TeX">${\rm kA/cm}^{2}$</tex></formula> HYPRES process for superconductor integrated circuits. Experimental results on adhesive-bonded and reflow-bonded multi-chip modules (MCMs) with Au and InSn bumps are presented, and effective parameters of the new interconnect design and MCM technology are discussed. </para>

Movement of solder fillers because of the unevenness of interfacial tension in self-organization assembly process

Soldering or anisotropic conductive adhesives (ACAs) are used for assembling of devices with high-density area-array terminals. However, solder bump processes are high-cost and interconnects of ACAs are less-reliable. The purpose of this study is to develop a novel method. Self-organization assembly method that uses active resin containing solder fillers may allow reliable interconnects at low-cost. Fundamental process of Self-organization assembly are movement, coalescence, and wetting of molten fillers in resin. The focus of this paper is on the movement of fillers. In-situ observations of coalescence behavior for 40μmϕ molten fillers in the resin revealed irregular movement of the fillers at a velocity of several μm/s. Numerical analysis, using improved volume fraction method, indicated that a 10% degradation of interfacial energy on one side of a 40μmϕ filler could move the filler at a velocity of several mm/s. This degradation of the interfacial energy was resulted the remaining oxide film.

Impact reliability estimation of lead free solder joint with IMC layer

To secure the reliability of lead free solder is a critical issue for a chip-scale packaging process. While lots of researches on the solder reliability have been conducted by applying numerical simulation techniques, researches on IMC (intermetallic compound) are not intensively condoned due to its thin thickness, geometric irregularity and so on. However, the IMC layer which is generated during the solder bumping process between solder and substrate is known as a key material determining the failure of solder joint. In this paper, the failure mode of solder joint is investigated by simulating the board level drop test which is described in the JEDEC standard. In this context, the IMC layer is produced by an ENEPIG process. Material properties of the IMC layer are obtained by performing a nano-indentation test for several points in the IMC region and the resulting test data are used for 3-dimensional finite element analyses to simulate the failure behavior. As a result, the solder joint corresponding to ENEPIG(0.1/0.8/0.12) surface finishing shows more resistant tendency against the drop impact failure than any other solder joint owing to a strain softening effect prior to the failure. The solder joint corresponding to ENEPIG(5/0.4/0.12) surface finishing, however, shows a sudden brittle failure mode due to the brittle characteristics of Nickel layer.

An empirical study on the robust design of a semiconductor-bumping process

Based on empirical data collection, computer simulation, statistical methods, and optimization techniques, this paper presents a study on optimizing the parameters of the solder bumping process in semiconductor fabrication (FAB). The research first collects a set of experimental data from the production site at the FAB. In this research, the experimental data of interest include bump height (BH) and bump shear (BS). Then, the researchers use the regression method for the experimental data on controllable factors to build an empirical model for problem analysis. The resulting empirical model is used to generate a set of experimental data to determine the critical controllable factors by design of experiments (DOE). Based on these empirical models, the optimum parameter values of controllable factors are found by optimization techniques such as mathematical programming. Because there are two quality characteristics, of interest in this research, a sensitivity analysis is performed during the problem analysis. As a result, a robust parameter design for quality improvement can be achieved for process design and planning.

Analysing inspection frequency for wafer bumping process and an empirical study of UNISON decision framework

This study aims to develop a UNISON decision framework for analysing the inspection frequency decisions for the advanced wafer bumping process. Since the accumulated values of the wafers fabricated in wafer fabs are high, process excursion and defects in bumping will cause serious loss. Thus, it is critical to determine the inspection frequency to fulfil the requirement of mass production while ensuring the yield. For validation, an empirical study was conducted in a bumping company and the results showed practical viability of the proposed approach.

A novel bumping process for fine pitch Sn–Cu lead-free plating-based flip chip solder bumps

Electroplating is the best process for the manufacture of fine pitch flip chip solder bumps. However, certain unstable electroplating parameters usually cause poorer coplanarity, which affects packaging reliability and yield. This paper attempts to utilize a CMP-like polisher to reduce the nonuniform height deviation after electroplating. The optimization of three major polishing parameters—pad hardness, loading pressure, and polishing speed—enables the polisher to have a higher material removal rate (MRR) and an easier manipulation as compared with chemical mechanical polishing (CMP). After polishing at a pitch size of 100 μm, the overall coplanarity could be decreased sharply from 33±2.5 μm (coplanarity=7.5%) to 28±1 μm (coplanarity=3%) and it even reached 26±0.5 μm (coplanarity=1%) after reflow.

Bump Formation and Flip Chip Processes for RF System-on-Packages

For flip-chip process of RF system-on-packages(SOP), double bump bonding processes were investigated. Sn-Ag and Sn solder joints were formed by the reflowed double bumping process, and Sn/In/Sn bump joints were fabricated by the non-reflowed double bump bonding process. The height-to-size ratios of 0.78 and 0.65 were obtained for the reflowed double bumping and the non-reflowed bumping, respectively. Average contact resistance of the reflowed Sn-Ag and Sn solder joints was about 13m/ which was much lower than 24~33m/ of the non-reflowed Sn/In/Sn bump joints. The reflowed solder double bumping method is more suitable for flip-chip process of RF-SOP than the non-reflowed double bump bonding.

Prediction of Solder Bump Formation in Solder Jet Packaging Process

Precise solder bump shape prediction is crucial for the application of the solder jet bumping process to microelectronic component packaging. In the present study, numerical simulation of both the dynamics and phase change responses during a metal droplet impingement is conducted by introducing a nonconstant interfacial heat transfer coefficient, which varies with time and position. Comparison between the numerical and experimental results for a large metal droplet demonstrates the validity of the numerical method. The results of many simulation cases are presented corresponding to typical solder jet bumping conditions. Variations in the impact velocity, initial droplet size, and droplet temperature and substrate temperature are investigated to understand their impact on the formation of solder bumps

Electromigration degradation mechanism for Pb-free flip-chip micro solder bumps

The electromigration (EM) of flip chip interconnect composed of Pb-free SnAgCu micro solder bump and Ni under bump metallization (UBM) is studied by accelerated current stress test. The process of void growth at the cathode side of the bump and resistance degradation process are investigated by physical analysis using SEM and Infrared microscope. EM degradation process for SnAgCu solder bump shows drastic change over time in degree of resistance shift owing to variation of contact diameter and UBM layer structure. UBM metal diffusion and local Joule heating caused by current crowding play important roles in voiding degradation process.

Data mining for improving the solder bumping process in the semiconductor packaging industry

AbstractModern semiconductor manufacturing is very complex and expensive. Maintaining high quality and yield enhancement have been recognized as important factors to build core competences for semiconductor manufacturing companies. Data mining can find potentially useful information from huge databases. This paper proposes a data‐mining framework based on decision‐tree induction for improving the yield of the solder bumping process in which the various (physical and chemical) input variables that affect the bumping process exhibit highly complex interactions. We conducted an empirical study in a semiconductor fabrication facility in Taiwan to validate this approach. The results show that the proposed approach can effectively derive the causal relationships among controllable input process factors and the target class to enhance the yield. Copyright © 2007 John Wiley &amp; Sons, Ltd.

THE DESIGN OF MASTER PRODUCTION SCHEDULING SYSTEM FOR BALL GRID ARRAY PACKAGING PROCESS

ABSTRACT The wafer bumping process in Ball Grid Array (BGA) packaging has three characteristics: long machine setup time, dynamical arrival of orders, and re-entrance of operations. These three properties make a factory with BGA packaging difficult to maximize its capacity utilization while having all orders meeting their due dates. Therefore, we design a master production scheduling (MPS) system for wafer bumping process which aims for having high due date achievement as well as doing customer order promising. The MPS system first estimates the cycle time roughly. Then a mixed integer programming (MIP) model is applied to optimize the setup schedule. With estimated cycle times and setup schedules, the master production scheduling system can plan master production schedules wich are capable to meet the due date requirement and can handle the task of customer order promising. The case studies show that this MPS system generates feasible master production schedules with high due date achievement.

Evaluation of displacement rate effect in shear test of Sn–3Ag–0.5Cu solder bump for flip chip application

An experimental investigation was combined with a non-linear finite element analysis using an elastic–viscoplastic constitutive model to study the effect of ball shear speed on the shear forces of flip chip solder bumps. A solder composition used in this study was Sn–3mass%Ag–0.5mass%Cu. A low cost bumping process has been employed using electroless Ni and immersion Au followed by solder paste stencil printing. A thin layer of intermetallic compound, (Ni 1− x Cu x ) 3Sn 4, was formed by the reaction between the solder and electroless Ni with a thickness of about 1.4 μm, while some discontinuous (Cu 1− y Ni y ) 6Sn 5 particles were also formed at the interface. The compositions of the resulting compounds were identified using energy dispersive spectrometer (EDS) and electron microprobe analysis (EPMA). Shear tests were carried out over a shear speed range from 20 to 400 μm/s at a shear ram height of 20 μm. The shear force was observed to linearly increase with shear speed and reach the maximum value at the fastest shear speed in both experimental and computational results. The optimum shear speeds for the shear test of solder bumped flip chip were recommended to be not exceeding 200 μm/s. The failure mechanisms were discussed in terms of von Mises stresses and plastic strain energy density distributions.

Experimental characterization and mechanical behavior analysis of intermetallic compounds of Sn–3.5Ag lead-free solder bump with Ti/Cu/Ni UBM on copper chip

Due to today’s trend towards ‘green’ products, the environmentally conscious manufacturers are moving toward lead-free schemes for electronic devices and components. Nowadays the bumping process has become a branch of the infrastructure of flip chip bonding technology. However, the formation of excessively brittle intermetallic compound (IMC) between under bump metallurgy (UBM)/solder bump interface influences the strength of solder bumps within flip chips, and may create a package reliability issue. Based on the above reason, this study investigated the mechanical behavior of lead-free solder bumps affected by the solder/UBM IMC formation in the duration of isothermal aging. To attain the objective, the test vehicles of Sn–Ag (lead-free) and Sn–Pb solder bump systems designed in different solder volumes as well as UBM diameters were used to experimentally characterize their mechanical behavior. It is worth to mention that, to study the IMC growth mechanism and the mechanical behavior of a electroplated solder bump on a Ti/Cu/Ni UBM layer fabricated on a copper chip, the test vehicles are composed of, from bottom to top, a copper metal pad on silicon substrate, a Ti/Cu/Ni UBM layer and electroplated solder bumps. By way of metallurgical microscope and scanning-electron-microscope (SEM) observation, the interfacial microstructure of test vehicles was measured and analyzed. In addition, a bump shear test was utilized to determine the strength of solder bumps. Different shear displacement rates were selected to study the time-dependent failure mechanism of the solder bumps. The results indicated that after isothermal aging treatment at 150 °C for over 1000 h, the Sn–Ag solder revealed a better maintenance of bump strength than that of the Sn–Pb solder, and the Sn–Pb solder showed a higher IMC growth rate than that of Sn–Ag solder. In addition, it was concluded that the test vehicles of copper chip with the selected Ti/Cu/Ni UBMs showed good bump strength in both the Sn–Ag and Sn–Pb systems as the IMC grows. Furthermore, the study of shear displacement rate effect on the solder bump strength indicates that the analysis of bump strength versus thermal aging time should be identified as a qualitative analysis for solder bump strength determination rather than a quantitative one. In terms of the solder bump volume and the UBM size effects, neither the Sn–Ag nor the Sn–Pb solders showed any significant effect on the IMC growth rate.

Low-cost wafer bumping

As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping processes have been developed to produce the small solder features required for this interconnect technology. These processes differ significantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 µm on 150-µm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.

Process optimization of gold stud bump manufacturing using artificial neural networks

The optimal operating conditions of a gold stud bumping process were determined using a process optimization scheme for a microelectronic packaging foundry. The schematic procedure of the process optimization is first to evaluate effects of the operating parameters on bump size and height, and shear stress, using a design of experimental method. Several operating parameters, such as compression force (bonding load) and electronic flame off (EFO) current and time, were analyzed to affect the formation of the stud bump significantly in the bumping process. Artificial neural networks (ANN) modeling was adopted to establish the relationship between the operating parameters and the bump properties with the experimental data. Some optimization cases of the bumping process with constraints were evaluated using the optimization scheme.