Bumping Process Research Articles

Fine-Pitch Copper Nanowire Interconnects for 2.5/3D System Integration

Heterogeneous integration is a key driver within the field of advanced electronic packaging. The realization of tomorrow’s highly integrated electronic systems depends on the combination and compatibility of various integration technologies at the same hierarchy level. The adoption of novel bonding technologies for a cost-effective realization of multi-chiplet systems is a key aspect. Cu nanowire (NW) interconnects exhibit distinct advantages in terms of their scalability down to a few micrometers, the resulting joint properties and moderate demands with respect to the surface preparation, and the cleanliness of the bonding environment. No solder or flux is required for the bonding process, but the NW bumps still can compensate low height differences. The bonding process can be carried out near room temperature under ambient conditions. We demonstrate the technological possibility to integrate the Cu-NWs for a bump processing scheme including the Cu seed etching on 300 mm wafer for the first time. This paper focuses on the microstructure evaluation and the shear test of the formed Cu-NW interconnects fabricated under ambient conditions within a few seconds. The microstructure analysis shows the intact bonded interconnects and reveals high-resolution details of Cu-NWs. The shear strength of the formed interconnects varies between 4.6 MPa and 90.5 MPa depending on the bonding and annealing conditions. Overall, the results of this study highlight the potential of Cu-NW interconnects for future 3D heterogeneous system integration.

High density fabrication process for single flux quantum circuits

We implemented, optimized, and fully tested a superconducting Josephson junction fabrication process over multiple runs tailored for integrated digital circuits that are used for control and readout of superconducting qubits operating at millikelvin temperatures. This process was optimized for highly energy efficient rapid single flux quantum (ERSFQ) circuits with critical currents reduced by a factor of ∼10 as compared to those operated at 4.2 K. Specifically, it implemented Josephson junctions with 10 μA unit critical current fabricated with 10 μA/μm2 critical current density. In order to circumvent the substantial size increase in the SFQ circuit inductors, we employed an NbN high kinetic inductance layer with 8.5 pH/sq sheet inductance. Similarly, to maintain the small size of junction resistive shunts, we used a non-superconducting PdAu alloy with 4.0 Ω/sq sheet resistance. For integration with quantum circuits in a multi-chip module, 5 and 10 μm height bump processes were also optimized. To keep the fabrication process in check, we developed and thoroughly tested a comprehensive process control monitor chip set.

An Evaluation of Bath Life Effects on Photoresist Removal for Wafer Level Packaging

With the emergence of 3D integration and wafer level packaging, the pillar bumping process has become a critical processing step. As the process has matured, significant efforts have been made for optimization in terms of both production and cost. This is especially true for photoresist stripping, since thick photoresists are needed to pattern high aspect ratios and must be removed in subsequent steps to expose underlying metal films. In this study, the removal of a thick negative tone photoresist with solder pillar plated wafers were investigated using a dimethyl sulfoxide blend with a quaternary ammonium hydroxide. Emphasis was placed on exploring the feasibility of an extended bath life beyond 7 days. Coupon level beaker tests were used to provide insight into the swelling and dissolution mechanisms with fresh and aged chemistry. Additionally, several chemistries were compared to examine the effect of the quaternary ammonium hydroxide. Based on these findings, chemical aging studies were performed on 300 mm wafers using a highly customizable single wafer processing tool that combined soaking and a high-pressure spray processing to potentially prolong the bath age even further. In addition to stripping efficiency at extended bath life, the compatibly with pillar structures and seed layers is investigated. Results from the study highlight potential methods to extend bath life while maintaining photoresist stripping efficiency.

Study on CPI behaviors of X Dimension Fan-Out Integration (XDFOI) packages

XDFOITM (X Dimension Fan Out Integration) is a package family designed for fan out packages and heterogeneous integration, as XDFOI offers great flexibility to let single die or multi-functional chips, such as logic, memory, power management, RF and passive components, to be packaged by technology evolutions. Based on the approaches of “chip first” and “chip last” processes, XDFOI is designed with the high density I/O and multi-layer metals, polyimide and encapsulation materials like ABF, underfill or molding compound. Various materials applied in the full process flow brings lots of combination of CTE (coefficient of thermal expansion) and meanwhile the CTE mismatch may generate stress on the dielectric materials to influence the performance requirements. It is widely known that manufacturing procedures of heterogeneous integration make the boundaries of foundry backend process of line (BEOL) and bumping process fuzzy. In this paper, three package members in XDFOI family are introduced and the respective process flows are illustrated detailed in order to exhibit the differences between the solutions. Finite-element analysis is integrated along with package building process to predict the stress performances. The simulation results of XDFOI packages divided by packages provide a guideline for estimating maximum stress on the dielectric materials. In order to provide proper guideline to chip packages, data from theoretical calculation are collected, analyzed and merged into design rules for further process optimization and new product introduction. It is considered that the study can greatly improve the overall innovation level and process capabilities.

Laser-Assisted Micro-Solder Bumping for Copper and Nickel-Gold Pad Finish.

Flip-chip bonding is a key packaging technology to achieve the smallest form factor possible. Using copper as a direct under-bump metal and performing bonding under little force and at a low temperature eliminates the processing step for the deposition of a suitable wetting metal and offers an economical solution for electronic chip packaging. In this paper, various samples with copper and nickel–gold surface finishes are used to apply an in-house solder bumping, flip-chip bonding and reflow process to exhibit the bump-bond feasibility. Native oxides are reduced using process gases, and copper surface protection and solder wetting are achieved using copper formate. Lead-free 40 µm solder balls were bumped on 80 µm copper pads and 120 µm copper pillars to demonstrate a full intermetallic Cu–Cu bond as a base study for stacking applications. Using a low-force bonding technique, various chips with different dimensions were bonded at 0.5–16 MPa, followed by a reflow step at a maximum temperature of 270 °C. Then, 30 µm solder balls are utilized to bump the samples with NiAu and Cu bond pads at 50 µm pitch. A mean shear strength of 44 MPa was obtained for the 30 µm Cu samples. To the best of our knowledge, 30 µm solder bumping directly on the copper pads by producing copper formate is a novel research contribution.

Implementation of Flip-Chip Microbump Bonding between InP and SiC Substrates for Millimeter-Wave Applications.

Flip-chip microbump (μ-bump) bonding technology between indium phosphide (InP) and silicon carbide (SiC) substrates for a millimeter-wave (mmW) wireless communication application is demonstrated. The proposed process of flip-chip μ-bump bonding to achieve high-yield performance utilizes a SiO2-based dielectric passivation process, a sputtering-based pad metallization process, an electroplating (EP) bump process enabling a flat-top μ-bump shape, a dicing process without the peeling of the dielectric layer, and a SnAg-to-Au solder bonding process. By using the bonding process, 10 mm long InP-to-SiC coplanar waveguide (CPW) lines with 10 daisy chains interconnected with a hundred μ-bumps are fabricated. All twelve InP-to-SiC CPW lines placed on two samples, one of which has an area of approximately 11 × 10 mm2, show uniform performance with insertion loss deviation within ±10% along with an average insertion loss of 0.25 dB/mm, while achieving return losses of more than 15 dB at a frequency of 30 GHz, which are comparable to insertion loss values of previously reported conventional CPW lines. In addition, an InP-to-SiC resonant tunneling diode device is fabricated for the first time and its DC and RF characteristics are investigated.

A Review on the Fabrication and Reliability of Three-Dimensional Integration Technologies for Microelectronic Packaging: Through-Si-via and Solder Bumping Process

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.

Characterization of sintered Cu nanopaste for micro-bumping with Injection Molded Solder technology

Abstract We have previously developed a novel plating-free bumping process using Cu nanopaste and Injection Molded Solder (IMS) technology. In the present study, we investigated the further detail about the microstructural and mechanical properties of sintered Cu nanoparticles formed into a pillar shape. By analyzing cross-sections of Cu nanoparticle pillars sintered in various conditions, we clarified how the sintering conditions affect the microstructural features, including the size and numbers of Cu grains and voids inside sintered Cu nanoparticles. In addition, we conducted the shear testing for the obtained Cu pillars to evaluate relationships between the mechanical strength and the microstructural features. We found that the results of the shear testing were consistent with the microstructural features of the sintered Cu nanoparticles. Finally, we injected molten solder onto the Cu nanoparticle pillars to evaluate the overall feasibility of the developed process. It was confirmed that the molten solder injected by IMS process has good wettability against the sintered Cu nanoparticles, which resulted in the successful bump formation without solder missing. In addition, The IMC layer between the sintered Cu nanoparticles and injected solder was formed well. These results proved the quality of microbumps fabricated by the novel bumping process using Cu nanopaste and IMS.

Bumping Co-planarity Collocation for Different UBM Size by Geometry Integration

Abstract Bumping co-planarity is a Cu pillar bump characteristic, that can impact to the joint quality of subsequent flip chip bonding process. The plated bump height variation correlates with lesser co-planarity values. Co-planarity can be minimized by bumping process, however the bumping process window is not adequate for some design features. For example, dummy bump or structure drawback features. This paper provides a methodology to improve co-planarity by collocating oval and circular bump which integrates the solder volume of different bump shapes. The final solder formation is different due to the geometry variation from the oval shape and circular shape. The final solder height can be calculated by mathematical integral from as-plated solder volume. Hence, better co-planarity can be achieved by the proposed method to collocate different bump shapes. The Cu pillar bump collocation design rules can be optimized to minimize co-planarity during initial design realization to minimize quality risks during fabrication..

Control of Solder Bump Growing Morphology in Lead Free Plating

Abstract Plating Solder bump is one of the key enabling technologies for flip chip assembly methodology. Flip chip assembly has advanced to support higher levels of interconnect and small feature sizes. Electroplating is a very promising technology for finer bump features when compared with solder printing and ball mounting. Hence, the plated-solder bump morphology is quite important for process quality control and design realization. This paper aims to study the plated solder behavior from as-plated mushroom structure to after reflowed bump stage photoresist sizing. In addition, this activity will consider the full bumping process integration relative to the electroplated solder bump design rules.

IMPROVE CONTROL AMIDST DIE SHRINKAGE AND 3D PACKAGE COMPLICATION

Abstract Die sizes continue to shrink and packaging technologies continue to evolve, but the common thread for all of them is the need for increased precision and tighter process control limits to achieve final package yield. Nearly all packaging technologies require connections in the third dimension, above or below the die, thus adding, quite literally, a new dimension to inspection and metrology requirements. Increased focus on reliability for automotive, health care and even mobile electronics is driving the need for improved process control solutions. The combination of higher packaging complexity and the need for improved reliability are driving changes to the requirements around inspection and metrology. Vertical integration continues to grow at a pervasive rate and the need for improved process control in the third dimension is growing rapidly in order to ensure reliability. Vertical integration is designed into nearly all packaging forms, including TSV, RDL, WLP, Fan-in, Fan-out, with a focus on continued increase in the number of I/Os, the pitch of features (RDL and bump) and the overall package size increasing. This integration drives the need for 3D metrology of feature height and coplanarity. In addition, the need to augment raw 3D metrology with defect inspection and 2D metrology data enables a comprehensive view (insight) into the packaging process. Achieve total bump process control with the combination of data from: (1) 2D defect detection – voids and shorts, foreign material, misprocessing; (2) 2D metrology – bump diameter, bump position, bump presence; (3) 3D inspection – bump too tall, bump too short, statistical process control (SPC); (4) Auto classifications – data must make sense and be easy to interpret. By combining high speed 2D, 3D metrology with defect inspection and advanced analytics, the quality of process control data can be exponentially improved to enable quick time-to-results for both process development and HVM control. This paper describes the inspection and metrology challenges of bumps in advanced packaging and the next generation high-throughput bump inspection methodology for wafers with extremely high bump counts as well as the data analysis

An Improved Manufacturing Yield Measure for Gold Bumping Processes With Very Low Nonconformities

Nowadays, thinner and slimmer smartphones have been widely applied in daily life. In most portable devices, liquid-crystal display driver integrated circuit (IC) or new touch display driver IC are critical components, in which the gold bumping process is used as an essential interconnection technology and usually outsources to out-sourced assembly and testing factories. In semiconductor packaging manufacturing, due to popular high-definition requirements of display devices, gold bumping processes require very low fraction of nonconformities. For this reason, accurately evaluating the manufacturing yield is very important to guarantee the quality requirements being met. To evaluate the yield of gold bumping processes, the most popular yield index $C_{\textrm {pk}} $ is widely employed in outsourcing contract arrangements. However, the typical existing nature estimator is a biased estimator and more conservative. In this paper, we provide an unbiased estimator to evaluate the gold bumping manufacturing yield more accurately. Based on the new estimator, we further propose a weighted parametric bootstrap method to obtain a reliable lower confidence bound that is closer to the true manufacturing yield. The new yield assessment can avoid underestimating the gold bumping manufacturing yield and can make more reliable decisions.

FCCSP IMC growth under reliability stress follows automotive criteria

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

Bumping Process Impact on the Chip Package Interaction (CPI) Reliability

Abstract Flip chip technology is widely used in advanced integrated circuit (IC) package. Chip package interaction (CPI) became critical in flip chip technology that needed to be addressed to avoid electrical or mechanical failure in products. When addressing CPI challenges, different areas have to be considered, ranging from silicon BEOL design and processing, bumping design and process, package assembly process, assembly bill of material (BOM), and substrate technology. Controlled collapse chip connection (C4) bump technology provided the inter-connection between the IC to package substrate for high-performance, leading-edge microprocessors. It is very critical for chip package interaction (CPI). With the transfer to lead free technology, bumping process plays more and more important role for chip package interaction reliability. In this paper, we focused on bumping process effect on the CPI reliability. The bumping process has been reviewed and CPI reliability issues induced by the bumping process like particles, Ti seed layer deposition, UBM undercut, Cu pad oxidation and contamination, photoresist opening damage have been discussed. Bumping process optimization and corrective actions have been taken to reduce those defects and improve CPI reliability.

Inkjet printed metallic micropillars for bare die flip-chip bonding

Inkjet printed metal micropillars have been developed to help meet the demands for novel and highly adaptable microelectronics fabrication processes. The digitally printed silver pillar arrays in this study have been utilized in place of wafer-level solder bump processes or chip-level wire-bonded stud bumps. These three-dimensional silver pillars were printed with a drop-on-demand piezoelectric inkjet printer utilizing silver nanoparticle ink. The inkjet printed micropillars were found to have 22 μm diameters and a height equivalent to approximately 3 μm per droplet. In our study, we chose pillars for further use as stud bumps with 8, 10, 12 and 14 droplets, with heights of approximately 20.9 μm, 25.9 μm, 33.3 μm and 35.9 μm respectively. After printing on the bare dies the bumps were subsequently used to increase the contact reliability of flip-chip bonded samples. It was found that the bumped chips dramatically improved the reliability of the I/O connection as compared to unbumped samples. In fact nearly 88% of the bumped pads had a resistance less than 2.5 Ω/bump (no noticeable variation between bump heights) as compared to 17% for the unbumped bare dies. This study clearly demonstrates the fabrication of inkjet printed silver micropillars for use in uniform stud bump arrays. Furthermore, the feasibility of incorporating inkjet printed silver stud bumps for use in flip-chip fabrication methods was demonstrated.

High Reliability and High Throughput Ball Bumping Process Solution – Solder Joint Encapsulant Adhesives

Abstract The miniaturization of microchips is always driving force for revolution and innovation in the electronic industry. When the pitch of bumps is getting smaller and smaller the ball size has to be gradually reduced. However the reliability of smaller ball size is getting weaker and weaker, so some traditional methods such as capillary underfilling, corner bonding and edge bonding process have been being implemented in board level assembly process to enhance drop and thermal cycling performance. These traditional processes have been increasingly considered to be bottleneck for further miniaturization because the completion of these processes demands more space. So the interest of eliminating these processes has been increased. To meet this demand, YINCAE has developed solder joint encapsulant adhesives for ball bumping applications to enhance solder joint strength resulting in improving drop and thermal cycling performance to eliminate underfilling, edge bonding or corner bonding process in the board level assembly process. In this paper we will discuss the ball bumping process, the reliability such as strength of solder joints, drop test performance and thermal cycling performance.

A review of soft errors and the low α-solder bumping process in 3-D packaging technology

This study reviews soft errors in modern electronic assemblies, through silicon via (TSV), and low α-solder bumping techniques for 3-D microelectronic packaging. The TSV fabrication involves deep reactive ion-etching process of Si wafers to form vertical holes, which are further filled with copper and joined to solder bumps. The solder bumps in close proximity to Si die thus impose a serious threat of soft errors. These soft errors responsible for the malfunction of electronic systems have become a critical issue in miniaturized and high-density packaging, like 3-D packaging. Various low α-solder bumping techniques have been reported to minimize these errors in modern microelectronic devices. A low α-solder is one that has low levels of α-particle emission, as compared to the conventional solder. In addition, it improves the performance and reliability of the solder joints, prompting the need to adopt low α-solder for bumping in TSV packaging. Thus, this paper discusses the various aspects of TSV fabrication, functional layer deposition, Cu filling into TSV, and low α-solder bumping on TSV by solder ball reflow methods.

Development of Advanced Manufacturing Cloud of Things (AMCoT)—A Smart Manufacturing Platform

As semiconductor manufacturing processes are becoming more and more sophisticated, how to maintain their feasible production yield becomes an important issue. Also, how to build a smart manufacturing platform that can facilitate realizing smart factories is essential and desirable for current manufacturing industries. Aimed at addressing the above-mentioned two issues, in this letter, a five-stage approach for enhancing and assuring yield is proposed. Also, a smart manufacturing platform- Advanced Manufacturing Cloud of Things (AMCoT) based on Internet of Things, cloud computing, big data analytics, cyber-physical systems, and prediction technologies is designed and implemented to realize the proposed five-stage approach of yield enhancement and assurance. Finally, AMCoT is applied to a bumping process of a semiconductor company in Taiwan to conduct industrial case studies. Testing results demonstrate that AMCoT possesses capabilities of conducting total inspection in production, providing prognosis, and predictive maintenance on equipment, finding the root cause of yield loss, and storing and handling big production data, which as a whole is promising to achieve the goal of zero defects.

Effects of Silicon Wafer Bump Pad Structures on Solder and Cu Pillar Flip-Chip Reliability

Abstract Solder and Cu pillar flip-chip silicon die technologies have been widely used in chip to package mobile module products. During the early design phase, integrated circuit (IC) designers usually apply standard bump design rules, due to lack of information on the reliability of the metal layer stack-up with different bumping processes. However, module reliability data has demonstrated that the stack-up and thickness of the metal layers in a silicon die has a great effect on package stresses, especially for large area Cu pillar flip chip die. In this paper, the effects of bump pad structures on solder and Cu pillar bump reliability have been investigated. A 3D mechanical stress model was developed to compare and optimize various bump structures. A test vehicle with die and module was designed and assembled in a volume production environment. Assembly in-line data was collected and analyzed, and is presented in this paper. Reliability testing and failure analysis were performed to verify the failure modes. Guidelines for designing solder and Cu Pillar Flip-chip bump pad structures have been developed, and are presented in this paper.

Group Supplier Selection for Multiple-Line Gold Bumping Processes

Portable devices have been popularly used nowadays. Liquid crystal display driver integrated circuit is an essential component in portable devices in which gold bumping process is a critical interconnection technology. To enhance bargaining power and to reduce cost, group suppliers are commonly selected from multiple suppliers. For high-definition display devices, a very low fraction of defectives is the basic quality requirement in gold bumping processes. Unfortunately, conventional yield measurement methods for supplier selection no longer work since any sample of reasonable size probably contains no defective gold bump product items. In this paper, we propose a group supplier selection procedure for multiple suppliers with multiple-line processes that are quite common due to high demands in semiconductor industry. For various significance levels, the number of suppliers, the number of manufacturing lines, predetermined capability requirements, and sample sizes, different selected suppliers are suggested based on the multiple-line yield index $C_{pk}^{M}$ . In addition, the power comparisons between different methods are also discussed. For the illustration purpose, real-world applications in a gold bumping factory that is located in the Science-Based Industrial Park in Hsinchu, Taiwan, are included.