Bulk CMOS Research Articles

A 1-A Switching LDO With 40-mV Dropout Voltage and Fast DVS

This brief presents a 1-A fully-integrated switching LDO for digital loads. By using 4-phase 200-MHz pulse-width modulation (PWM), it can significantly reduce the output ripple and allow using a smaller output capacitor. Distinctive from the prior dual-loop structure, we adopt a single feedback loop with a wide bandwidth error amplifier (EA) using a quasi-Type-III compensation to improve the dynamic voltage scaling (DVS) rate and to reduce the transient recovery time. Meanwhile, compared with the prior stacked power transistor architecture, the single-PMOS with auxiliary constant current (ACC) control can reduce by 4-fold the power transistor size, and decreases the driver current by at least 2.5 times. Fabricated in 28-nm bulk CMOS, the proposed LDO measures a 1-A load capability with a 40-mV dropout voltage. Moreover, the measured load regulation is 2.2 mV/A, and the line regulation is 1.8 mV/V. In addition, the regulator obtains a fast DVS speed of 4V/μs and a fast load transient recovery time of <50ns.

185–215 GHz CMOS Frequency Doubler with a Single Row Staggered Distribution Layout Design

This paper presents a 220 GHz × 2 amplifier–doubler chain composed of a rat-race balun, a 6-stage driver amplifier, and a frequency doubler. The presented amplifier–doubler chain was fabricated in commercial 40 nm bulk CMOS technology. The maximum cutoff frequency fmax for the NMOS transistor produced by this manufacturing process was 290 GHz. The saturation output power of the six-stage driver amplifier at 110 GHz was 11.5 dBm. The transistor of the frequency doubler consisted of a single-row interleaved Poly-Diffusion Contact balancing structure. Theoretically, the single-row interleaved Poly-Diffusion Contact balancing structure was able to effectively avoid parasitic components. The simulated results demonstrate that the presented structure achieves a higher output than the conventional designs. Based on these measured results, the presented amplifier–doubler chain provides a peak output power of 7.9 dBm at 200 GHz and a 3-dB bandwidth of 30 GHz. Based on the comparison with other reported results, the presented amplifier–doubler chain provides the highest output power among reported frequency doublers fabricated in CMOS technology.

A 52–65 GHz Frequency Quadrupler With Low Conversion Loss and High Harmonic Rejection Ratio in 28-nm CMOS

This brief presents a 52-65 GHz frequency quadrupler with low conversion loss and high harmonic rejection ratio based on 28-nm bulk CMOS process. The frequency quadrupler includes two stages balanced frequency push-push doublers (PPD) cascaded with common-gate buffers. A series LC pair is placed between the PPD and the buffer of the first stage, which not only improves the conversion gain, but also suppresses the unwanted fundamental signals. A filter-integrated matching network is designed as the output matching network to reject undesired harmonics. As a result, the proposed design exhibits advantages in conversion gain and harmonic rejection ratio. The measured peak output power is -1.8 dBm and the output power 3-dB bandwidth is 52-65 GHz when the input power is 0 dBm. The even and odd harmonics rejection ratios are better than 35 dBc and 45 dBc, respectively, which can be used in high-performance mm-Wave LO chain.

A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation

This brief proposes a fully dynamic discrete-time (DT) Σ ADC using a correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS-assisted FIA improves amplifier gain with a single-stage configuration, which has lower input-referred noise than the cascaded one. In combination with the proposed SNC, the noise contribution of the 1st-stage integrator can be minimized. We also propose a novel passive integrator cascaded with a passive adder that avoids unwanted inter-stage loading without a speed penalty. The prototype of the proposed ADC fabricated in a 65 nm bulk CMOS process realizes a fully dynamic operation and achieves 94.8 dB SNDR with an OSR of 256 for 19.5 kHz bandwidth while consuming 79.2 W from a 1.2V supply at a 10 MHz sampling frequency. The Schreier and Walden FoMs are respectively 178.7 dB and 45.2 fJ/conv.-step, which are the best among recent fully dynamic DT Σ ADCs with similar bandwidth.

A 28-GHz 26.8-dBm Doherty Power Amplifier With Four-Way Differential Hybrid Load- Modulated Combiner in 55-nm CMOS

This letter presents a 28-GHz high-power four-way differential Doherty power amplifier (PA) in 55-nm bulk CMOS technology. A transformer-based hybrid load-modulated combiner (HLMC) (i.e., a parallel combined series-load-modulated Doherty output network) is proposed to simultaneously achieve high output power, low-loss power combining, and a true-Doherty load modulation. Meanwhile, the closed-form expressions of the proposed combiner are derived. The measured results of the proposed Doherty PA demonstrate a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm{sat}}$</tex-math> </inline-formula> of 26.8 dBm, an output 1-dB compression point (OP1dB) of 25.2 dBm, a peak power added efficiency (PAE) of 26.7%, and 19.2% PAE at 6-dB power back-off (PBO) at 28 GHz. The PA is also tested with 400-MSym/s 64-quadrature amplitude modulation (QAM) signals, and it achieves 17.9-dBm average output power with 14.1% average PAE at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 26.2-dB error vector magnitude (EVM).

A Highly Efficient V-Band Dual-Harmonic-Driven Frequency Doubler

A V-band frequency doubler with a dual-harmonic-driven push-push core with a pair of accumulation-mode MOS (AMOS) varactors at the input is presented. The nonlinear characteristics of the varactor introduce 2f0 into the input, which is amplified and added to the rectified 2f0 at the output of the push-push core. This facilitates high DC-to-RF efficiency. AMOS varactors with odd symmetric C-V characteristics are used to efficiently create 2f0.The doubler is implemented in 28nm bulk CMOS technology, achieving an output power of -2.4 to 0.2 dBm and drain efficiency of 13.6 to 20.2% at frequencies of 50-64 GHz. The core size of the chip is 0.053 mm, which is the smallest among reported V-and E-band frequency doublers.

A Fully Integrated High Efficiency 2.4 GHz CMOS Power Amplifier with Mode Switching Scheme for WLAN Applications

A 3.3 V mode-switching RF CMOS power amplifier (PA) for WLAN applications is presented, which is integrated into a 55-nm bulk CMOS process. The proposed PA offers both static control and dynamic power control, allowing it to operate efficiently in both low-power and high-power modes. The pure low-power mode is achieved by reducing power cells, which are also used for linearization in high power mode. The low-power mode is achieved by reducing the number of power cells which are also used for linearization in the high-power mode. In the dynamic power control mode, the total AM–AM and AM–PM distortion is effectively compensated for by dynamically controlling the number of power cells and adjusting the matching input. The proposed PA achieves an output P1dB of 27.6 dBm with a PAE of 32.7% and an output P1dB of 17.7 dBm with a PAE of 10% in high-power and low-power modes, respectively. It is measured with an 802.11 n 64-quadrature-amplitude-modulation (MCS7) signal and shows a maximum average power of 19 dBm under an error-vector-magnitude (EVM) of −27 dB.

Verilog-A модель эффекта вымораживания примеси в LDD областях при криогенных температурах

The article shows the practical implementation of the impurity freeze-out effect in the lightly-doped areas of the drain and source (LDD) in the Verilog-A model of the resistor. This model is based on a theoretical understanding of the freeze-out effect at cryogenic temperatures and data from the TCAD simulation of a MOSFET. The TCAD simulation data were represented by transconductance characteristics of n- and p-channel transistors Id(Vg) in linear mode (Vd=0.1 V) at temperature range from -200 °C to 27 °C for transistors with dimensions 10 um × 10 um. The model is applicable to the use as part of a macromodel of a MOSFET transistor for a CMOS bulk process with a supply voltage of 1.8 V and a minimum channel length of 0.18 um. Since the model is based on a limited set of TCAD modeling data, this version is the basis on which it is possible to build a geometrically scalable model that will be valid over the entire range of drain voltages.

A 6–18 GHz bulk CMOS three-stage gain-compensation amplifier for phased-array radar system

A fully integrated 6–18 GHz bulk CMOS ultra-wideband (UWB) gain-compensation amplifier for phased-array radar system based on SMIC 40-nm CMOS process is presented in this paper. Combined with dual-branch input matching network, three-stage cascaded amplification and both the inductive series- and shunt-peaking techniques, the gain 3-dB bandwidth (BW) is further extended. The fabricated UWB amplifier achieves a flat gain of 8.7–13.3 dB and an averaged noise figure (NF) of 5.75 dB with input return loss better than −15.1 dB. Measured input 1-dB compression point (IP1dB) is −11.9 dBm at 12 GHz. The UWB amplifier totally consumes 33.6 mW from a 1.2-V supply and occupies an area of 0.337 mm2.

Bulk CMOS Low Noise Amplifier With Two Stage HPF Noise Matching Structure

In this study, a two-stage low-noise amplifier (LNA) was developed in which the noise-matching network of a high-pass filter (HPF) structure is applied to both stages. As the HPF noise matching network is used in both stages, the noise figure of the proposed LNA can be reduced compared to that of the conventional LNA. In particular, the noise figure is improved in the high-frequency region. To verify this development, a two-stage common-source LNA was implemented using 0.18-lm bulk complementary metal oxide semiconductor technology. The fabricated LNA achieved an average noise figure of 2.6 dB (minimum noise figure of 2.23 dB at 3.95 GHz) and a peak gain of 14.19 dB. In addition, the LNA has an input 1-dB compression point (IP1dB) of.12 dBm and a third-order input intercept point (IIP3) of +2.0 dBm at 3.5 GHz, consumes 16 mA with a 0.9 V supply, and has an area of 0.7 mm2.

Fully bulk CMOS compatible Key Shape Floating Body Memory (KFBM)

This paper presents a capacitorless memory cell with bulk CMOS compatibility, consisting of a MOSFET with a virtual floating body formed by the trench. The name Key shape Floating Body Memory (KFBM) is derived from the resemblance of the structure to the shape of an antique key. The carrier concentration in the vertical device beneath the MOSFET results in over more than 5 orders of magnitude of the on–off cell current ratio with off-current less than 100pA/cell. The device achieves a retention time of about 1 s at 85C and over 10 s at 27C all the while maintaining high density and scalability. On the basis of TCAD simulation we have demonstrated high tolerance to disturbance (more than 1000 times with all types of signals), which has been an issue with DRAM memories. KFBM can incorporate both dynamic RAM and flash features.

28 Gbaud PAM-4 Burst-Mode CDR With Reconfigurable Sampling Scheme

This paper presents a fast-locking 28 Gbaud PAM-4 CDR targeting for burst-mode operation. By implementing an oversampling scheme tailored for the preamble stage signal according to the pattern appearance regulation, the trade-off between the loop bandwidth and the convergence time in the conventional CDR is avoided. In addition, to reduce power consumption in the oversampling mode, a 3-phase sampling scheme equivalent to 3 times-oversampling with a minimal phase shift range of 30 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> is proposed. The PAM-4 burst-mode CDR also includes a conventional Bang-Bang phase locking loop with a bandwidth of 5 MHz. Realized in a 65nm bulk CMOS technology, the CDR chip achieves 28 Gbaud PAM-4 burst-mode clock recovery within 10 ns. With integrating slicers, phase interpolators and output buffers, the total power consumption of the CDR is 154 mW. Compared with the prior arts, to the best of authors’ knowledge, the proposed CDR first achieves on-chip phase-locking with PAM-4 Burst signals, based on the proposed PAM-4 burst-mode signal tailored 3-phase oversampling scheme.

A 124-to-152-GHz Power Amplifier Exploiting Chebyshev-Type Two-Section Wideband and Low-Loss Power-Combining Technique in 28-nm CMOS

This article presents a high-power wideband power amplifier (PA) with a four-way power-combining technique for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$</tex-math> </inline-formula> -band high-resolution radar. The power combiner is based on a two-section Chebyshev impedance converter to achieve a large bandwidth (BW) and is realized with slow wave coplanar waveguides (S-CPWs) to reduce the insertion loss and chip area. Therefore, our developed technique can provide broadband and low-loss power-combining scheme in a very compact size. A high-power PA with four-way combining has been fabricated in a 28-nm CMOS bulk technology. The unit PA uses low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$k$</tex-math> </inline-formula> transformer-based coupled-resonator networks to realize wideband matching. The measured results of the PA prototype demonstrate the peak gain of 22.6 dB, the saturated output power of 16.2 dBm, and the peak power added efficiency of 8.6% at 135 GHz with a 3-dB BW of 28 GHz from 124 to 152 GHz. Meanwhile, the total area of this PA die is merely 0.66 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 0.73 mm.

A V‐band digitally controlled low noise variable gain amplifier with 3.5° phase variation in 28‐nm bulk CMOS

AbstractThis paper presents a V‐band digitally controlled low noise variable gain amplifier (LNVGA) in 28‐nm bulk CMOS process. The amplifier includes three stages and the first stage is used to realize wideband high gain and low noise figure (NF). The gain control is implemented in the second and third stages with current steering and split cascode topology, respectively. A source degeneration inductor and a series inductor are introduced to reduce the phase variation in the second stage. The phase response function is analyzed, and the phase reduction of 1.2° is achieved. Moreover, with the combination of these two different topologies, the phase variation can be further reduced. The measurement results show the LNVGA has a peak gain of 16 dB with a 3‐dB bandwidth of 45–59 GHz. The measured gain control range is 0–16 dB in 16 different gain states and the minimum phase variation is 3.5° with power consumption of 23 mW.

VES-BJT: A Lateral Bipolar Transistor on SOI with Polysilicon Emitter and Collector

This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not only to make field effect transistors but also to make bipolar transistors. Their structures differ in many ways from existing structures of bipolar transistors. The investigations reported here aim to answer the question: can VESTIC-based lateral bipolar transistors be useful as active devices, and can they be made technologically compatible with field effect VESTIC devices? The theoretical studies were followed by the fabrication and measurements of VESTIC-based p-n-p and n-p-n bipolar devices. Although the manufacturing technology available was far from optimal, working bipolar devices were obtained. The results show that VESTIC-based bipolar devices may achieve acceptable parameters if made with state-of-the-art manufacturing technology. The main outcome of the research reported in the paper is that p-n-p and n-p-n bipolar transistors with acceptable parameters may be fabricated, together with field effect devices, in VESTIC-based integrated circuits. As a result, the VESTIC technology could become the new original BiCMOS technology.

28 GHz compact 4‐way Wilkinson power divider/combiner using RCIN and mutual inductors in 0.13 μm CMOS technology

AbstractIn this study, we proposed a 4‐way Wilkinson power divider/combiner (WPDC) with a series RC(resistor‐capacitor) isolation network (RCIN) and mutual inductors for millimeter wave phased array applications. The proposed circuit offers small chip sizes and low insertion loss, measuring less than 0.85 dB, as well as an input/output return loss greater than 11.8 dB. Additionally, simulations showed isolation greater than 18.7 dB, amplitude imbalance less than 0.026 dB, and phase difference less than 0.26° in the 26–32 GHz. The 4‐way WPDC was implemented using bulk CMOS 1P8M 0.13 μm technology and had a circuit size of 0.087 mm².

Effective Channel Mobility Extraction and Modeling of 10-nm Bulk CMOS FinFETs in Cryogenic Temperature Operation for Quantum Computing Applications

This article presents an extensive experimental investigation of transport properties in 10-nm CMOS Bulk FinFETs at cryogenic temperatures. The split-CV technique is employed to analyze the effective electron and hole mobilities from 300 to 10 K. Temperature and length dependence of effective mobilities is explored taking into account different scattering mechanisms. Hole mobilities were found to be dominated by temperature-independent neutral defects and surface scattering events for short-channel devices at low temperatures; while for electron mobilities, degeneracy effects at the cryo-temperature result in mobility enhancement at high fields. The short-channel devices show significant mobility degradation and weaker temperature dependence which could limit their utility for high-speed cryogenic-CMOS-based circuits. Variation of electrical parameters, such as subthreshold swing (SS), equivalent oxide thickness (EOT), threshold voltage, and effective length with temperature is also discussed. For accurately capturing the effective mobility trends in the specified temperature range along with the threshold voltage and SS trends, the existing BSIM-CMG 110.0.0 compact model equations are modified. The proposed model is validated across different device geometries of the short-channel bulk FinFETs fabricated with industry-standard 10-nm layout rules.

Characterization and compact modeling of short channel MOSFETs at cryogenic temperatures

This paper presents an overall characterization, physics-based device analysis, and compact modeling of a commercial 110nm bulk CMOS technology. I−V measurements and DC parameters extraction are performed on low threshold voltage (low VTH, LVT) and regular VTH (RVT) devices with various geometry dimensions from 300 K to 6 K. Different levels of improvement of subthreshold swing (SS), OFF-state current (IOFF), and mobility indicates the potential to optimize the performance of circuits at cryogenic temperatures. However, the temperature characteristics of the mobility and series resistance show a great dependence on the channel length of the devices, which complicates the calculation of the ON-state current at cryogenic temperatures. Moreover, VTH roll-off caused by short channel effect (SCE) get worse, which can be attributed to the increased bulk Fermi potential (ϕf). These channel-length-related effects add extra challenges to the design of cryogenic circuits. An optimized compact model based on BSIM4 is proposed to capture the device characteristics at 6 K, which can produce accurate simulation results only through parameter configuration rather than model equation modification and has been applied to the design of cryogenic CMOS circuits.

Compact size buck converter using small output capacitance with pole-tuning technique

This paper presents a compact buck converter using a pole-tuning technique in a 180-nm bulk CMOS process. The proposed pole-tuning technique enables the miniaturization of the output capacitor by reducing the required capacitance and improves the regulation characteristics by optimizing the inductor.The designed converter uses a high-speed switching frequency to reduce the inductor size, and by tuning the poles, the unity-gain bandwidth of the circuit is maintained. The ripple size owing to the reduced size of the capacitor showed a negligible change owing to the equivalent series resistance of the LCR filter.The designed buck converter uses an inductor of 0.1 μH and a capacitor of 0.1 μF. To apply a wide current range and high power efficiency, the converter has a load current range of 50–1000 mA and generates a voltage of 0.6–1.5 V with a source of 1.6–2.4 V. The designed buck converter was fabricated using a 0.18 μm CMOS. It operates at a switching frequency of 30 MHz, and the current ripple is within 15% under full load conditions. The converter exhibited a peak efficiency of 92.2% at 800 mA and conversion efficiency of over 76% over a load range of 50–1000 mA.

Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices

Atrial fibrillation (AF) is a recurrent and life-threatening disease leading to rapid growth in the mortality rate due to cardiac abnormalities. It is challenging to manually diagnose AF using electrocardiogram (ECG) signals due to complex and varied changes in its characteristics. In this article, for the first time, an end-to-end edge-enabled machine learning-based VLSI architecture is proposed to classify ECG excerpts having AF from normal beats. Researchers have found that abnormal atrial activity is confined to the low-frequency range through the decades. Therefore, in the proposed work, this frequency band is directly analyzed for AF detection, which has not previously been discussed. The proposed architecture is implemented using 180-nm bulk CMOS technology consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.098~\mu {\mathrm{ W}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25~ {\text {kHz}}$ </tex-math></inline-formula> and exhibits an accuracy of 92.37% for class-oriented classification and 81.60% for subject-oriented classification. The low-power realization of the proposed design, as compared to the state-of-the-art methods, makes it suitable to be used for wearable devices.