Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices

Abstract

Atrial fibrillation (AF) is a recurrent and life-threatening disease leading to rapid growth in the mortality rate due to cardiac abnormalities. It is challenging to manually diagnose AF using electrocardiogram (ECG) signals due to complex and varied changes in its characteristics. In this article, for the first time, an end-to-end edge-enabled machine learning-based VLSI architecture is proposed to classify ECG excerpts having AF from normal beats. Researchers have found that abnormal atrial activity is confined to the low-frequency range through the decades. Therefore, in the proposed work, this frequency band is directly analyzed for AF detection, which has not previously been discussed. The proposed architecture is implemented using 180-nm bulk CMOS technology consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$11.098~\mu {\mathrm{ W}}$ </tex-math></inline-formula> at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25~ {\text {kHz}}$ </tex-math></inline-formula> and exhibits an accuracy of 92.37% for class-oriented classification and 81.60% for subject-oriented classification. The low-power realization of the proposed design, as compared to the state-of-the-art methods, makes it suitable to be used for wearable devices.