Built-in Self-test Technique Research Articles

Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators

With increasing pressure to obtain near-zero defect rates, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, power converters, and data converters. This article presents an extremely low-cost built-in self-test technique for LDOs, specifically designed for fault detection. The methodology relies on exciting the LDO loop at the voltage reference input via a pseudo-random signal with white noise characteristics and observing the response from the output of LDO via all-digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with an LDO as a device under test is designed in 65nm technology. Fault simulations performed at the transistor level show that all resistive open/short defects in circuit components can be detected even if they do not cause a catastrophic failure in the LDO response. The proposed technique is validated with hardware using off-the-shelf components.

Power analyzer of linear feedback shift register techniques using built in self test

Wasteful patterns that don't lead to fault dropping squander a tone of energy in the linear-feedback shift register and circuit under examination in a random research region. Random switching actions in the CUT and scan pathways between applications with two consecutive vectors are another significant cause of energy loss. This study proposes a unique built-in self-test (BIST) technique for scan-based circuits that might help save energy. Only the available vectors are produced in a fixed series thanks to a mapping logic that alters the LFSR's state transitions. As a consequence, and without reducing fault coverage, the time it takes to execute trials has decreased. Experiments on circuits demonstrated that during random testing, the linear feedback shift register saves a significant amount of power.

Design of a BIST implemented AES crypto-processor ASIC.

This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.

Fault-based Built-in Self-test and Evaluation of Phase Locked Loops

With the increasing pressure to obtain near-zero defect rates for the automotive industry, there is a need to explore built-in self-test and other non-traditional test techniques for embedded mixed-signal components, such as PLLs, DC-DC converters, and data converters. This article presents a very low-cost built-in self-test technique for PLLs specifically designed for fault detection. The methodology relies on exciting the PLL loop in one location via a pseudo-random signal with noise characteristics and observing the response from another location in the loop via all digital circuitry, thereby inducing low area and performance overhead. The BIST circuit along with a PLL under test is designed in 65 nm technology. Fault simulations performed at the transistor and system-level show that the majority of non-catastrophic faults that result in parametric failures can be detected with the proposed approach.

CAN-Based Aging Monitoring Technique for Automotive ASICs With Efficient Soft Error Resilience

The modern automobile industry is rapidly shifting toward the era of self-driving cars. Due to rapid technological development, many mechanical parts in automobiles have been switched to electronic devices. Therefore, the proportion of electronic devices in modern cars is increasing. Even though many parts have been replaced by electronic devices, vehicles still require the periodic maintenance not only for mechanical parts, but also for automotive electronics. To guarantee the high reliability of automotive Application-Specific Integrated Circuits (ASICs), automotive chips are tested during manufacturing for functional and structural defects. Moreover, automobile chips are also tested using several in-field diagnostic techniques (e.g., online Built-In Self-Test (BIST), Software-Based Self-Test (SBST)) while the chips are operating. By using these in-field diagnostic techniques, functional and structural defects in automotive ASICs, which occur in the early-life cycle and normal operation, can be detected. However, automotive semiconductor devices still require testing for aging-induced defects and soft errors to prevent critical functional failures. Moreover, aging-induced defects are hard to detect with conventional in-field diagnostic techniques which is based on BIST techniques. Thus, this work presents a secure Controller Area Network (CAN) -based Test Access Mechanism (TAM) for aging defect diagnosis with efficient soft-error resilient scan cell design for automotive ASICs. The proposed TAM incurs area overhead of 6% to 9% depending upon the selection of mode identification. Further, the proposed Aging monitoring and Soft Error Resilience Flip Flop (ARFF) incurs 22% less area and power as compared to separate implementation of the Built-In Soft Error Resilience (BISER) and the Early Capture Flip Flop (ECFF).

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques.

Performance Analysis of BIST Algorithms

Objective: Performance analyses of March LR and March C- are presented to achieve high fault coverage, low power dissipation, less area utilization and minimum testing time. Methods: Testing of memory consist of Built-In-Self-Test (BIST) controller and circuit-under-test. BIST algorithms are resided inside the BIST controller. BIST algorithms such as March LR and March C- are coded in term of finite state machine. Memory is modeled in verilog and simulated in ModelSims for testing memory faults and it is synthesized by using Xilinx Vivado 2012.2 EDA tool for power, area and timing analysis. Findings: Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique. Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are Stuck-At Fault (SAF), Stuck Open Fault (SOF), Transition Fault (TF), Coupling Fault (CF) etc. These functional faults are model and write the code in verilog. Faults are inserted and detected using ModelSims. Using Xilinx Vivado 2012.2 EDA tool, power, area and timing are analyzed. Comparison is made between March C- and march LR. Even though March LR has more length (14N), it has high fault coverage and lesser power dissipation. Thus, March LR is more efficient than March C-. Applications/Improvements: The fault coverage is improved by using March LR. More improvement in March LR can detect more faults which result in the efficiency for online BIST. Keywords: BIST Algorithm, Built-In-Self-Test (BIST), March C- and March LR, Memory Testing

Time domain modelled ADC BIST with ramp noise projection

ABSTRACTThis paper proposes a time domain modelled built-in self-test (BIST) with ramp noise projection and their effects on analogue to digital converter (ADC) in testing. A self-biased linear ramp generator has been proposed for high precision testing. Threshold inversion quantization (TIQ) comparator based fast switching flash ADC has considered under test. A time domain model of output response analysis technique has been proposed to calibrate the linearity errors of the converter. An ADC has been validated with different input frequencies to characterize the harmonic distortion and average delay of the system. The proposed testing technique requires less time to measures the uncertainties of the ADC since the full computation is performed within one ramp cycle. The testing results of the proposed BIST technique are aimed to characterize, validate and compare to the best results of the existing ADC BIST techniques for test accuracy.

An ADC BIST using on-chip ramp generation and digital ORA

Abstract This paper presents an on-chip built-in self-test technique for testing an ADC. The conventional test of a mixed signal element has performed through DSP based tester with the help of an arbitrary waveform and a signal digitizer but it is consuming more time and cost. Hence, the testing strategy has started an on-chip BIST based testing scheme to control the testing issues. An on-chip ramp generator based BIST technique has proposed for testing static characteristics of ADC. The evaluation procedure of this BIST consists of test pattern generation and output response analysis. A novel cascode current mirror based analog linear ramp generator has used to generate the test pattern through fast switching TIQ comparator based ADC. Output response analyzer evaluates switching positions of binary code for computing the static parameters. The proposed ADC BIST has implemented in 0.18 μm technology with the supply voltage of 1.8 V.

A Brief Review for Semiconductor Memory Testing Based on BIST Techniques

With rapid growth of semiconductor industry and increase in complexity of semiconductor based memory, necessity of stringent testing methodology has become one of top most criteria for memory evaluation. This paper describes the fundamental concepts and overview of Built-In-Self-Test (BIST). It describes different functional faults modeling of RAM and flash memory. This review mentions about testing approaches for memory and illustrates BIST techniques for finding faults, power dissipation, area overhead and test time during testing, also includes research gap and future scope regarding the testing of memory.

A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters

Specifications of Radio Frequency (RF) analog integrated circuits have increased strictly as their applications tend to be more complicated and high test cost demanding. This makes them very expensive due to an increased test time and to the use of sophisticated test equipment. Alternative test measures, extracted by means of Built-In Self Test (BIST) techniques, are useful approaches to replace standard specification-based tests. One way to evaluate the efficiency of the CUT measures at the design stage is by estimating the Test Escapes (T E ) and the Yield Loss (Y L ) at ppm level. Unfortunately, an important number of Monte Carlo simulations must be run in order to guarantee their accuracy. For certain types of circuits, this requires many months or even years to generate millions of circuits. To overcome this limitation, we present in this paper a new technique where a small number of simulations is sufficient to reach an important precision. This method is based on a classification using machine learning methods, such as SVM and Neural Networks based classifiers to determine pass/fail regions. The proposed approach requires a few number of simulations only to determine the region separating the process parameters generating good and faulty, or pass and fail circuits. Then only this region is needed to estimate the test metrics without running any additional simulation. The proposed methodology is illustrated for the evaluation of a filter BIST technique.

Built-In Test of Phased Arrays Using Code-Modulated Interferometry

This paper presents a built-in self-test technique for phased arrays that applies code modulation to each element within the array to allow parallel in situ measurements and a built-in distribution network to allow injection or extraction of test signals. The aggregated test response is downconverted from radio-frequency or millimeter-wave frequencies using a direct (power) detector, resulting in a baseband interference signal composed of code-modulated complex cross correlations between all elemental signals. Using orthogonal code products, each cross correlation can be extracted from the interference signal, and then the full set of cross correlations can be used to obtain amplitude and phase data of each element. A four-element 60-GHz phased-array receiver front end that includes this code-modulated embedded test (CoMET) infrastructure has been fabricated in SiGe BiCMOS technology. The BIST overhead is less than 2% of the total die area. Comparisons between our built-in test technique and measurements using a vector network analyzer show that CoMET can be used to extract amplitude with 1 dB accuracy and phase with four degree accuracy. Furthermore, measurements confirm that CoMET can be used to extract the phase-step response of each element in parallel across all settings as well as phase offset introduced by the built-in test network.

Online Built-In Self-Test of High Switching Frequency DC–DC Converters Using Model Reference Based System Identification Techniques

A built-in self-test (BIST) technique that enables tracking of loop parameters of integrated DC–DC converters without affecting the normal mode of operation is presented. A digital pseudo-noise based stimulus and a mixed signal cross-correlation based analysis technique is used to derive on-chip impulse response, with minimum computational requirements in comparison to a digital correlator approach. Using measured impulse response, open-loop phase margin and closed-loop unity-gain frequency are estimated within 5.2% and 4.1% error, respectively, for the load current range of 30 mA to 200 mA. Converter parameters, such as natural frequency, $Q$ -factor, and center frequency are estimated within 3.6%, 4.7%, and 3.8% error, respectively, over load inductance of 4.7 $\mu \text{H}$ to 10.3 $\mu \text{H}$ , and filter capacitance of 200 nF to 400 nF. A 5 MHz switching frequency, 5 V to 8.125 V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed model reference based parametric and non-parametric BIST analysis. The converter output voltage range is 3.3 V to 5 V and supported maximum load current is 450 mA with a peak efficiency of 87.93%. The proposed converter is fabricated on a 0.6 $\mu \text{m}$ 6 layer-metal SOI technology with a die area of 9 mm2. The system identification circuitry occupies 3.8% of the converter area with 530 $\mu \text{A}$ quiescent current during operation.

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.

An FPGA Implementation of On Chip UART Testing with BIST Techniques

A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity characterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is conveniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST version of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor-level and behavioral-level simulations that employ actual production test data.

Prebond Testing of Weak Defects in TSVs

Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process to prevent stacking yield loss. Thus, the development of effective prebond testing techniques becomes of great importance. In this direction, recent research effort has been devoted to the development of two main prebond techniques: 1) prebond probing and 2) built-in self-test (BIST) techniques. The prebond probing poses economic and technological challenges, whereas current BIST proposals have disadvantages for certain solutions. Hence, there is still a need for an effective methodology in terms of fault coverage, area overhead, and test time. This paper proposes a BIST technique based on a simple unbalanced circuit comparing the behavior of two TSVs. Electrical simulation results show the viability of the proposal to detect weak defects, i.e., resistive opens and resistive bridges, adding reasonable area overhead in a short-test application time. Furthermore, an experimental design is built on a 65-nm technology, where resistive open defects are intentionally injected. Automated test equipment measurements confirm the simulation results.

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference

The direct radio frequency power injection (DPI) method was extended using on-chip voltage waveform monitoring and built-in self-test techniques. Static random access memory (SRAM) has been chosen as a demonstrator of the extended DPI method and exhibits a higher susceptibility against the lower interference frequency. This response is explained when we consider the time length of the threshold against how long the supply voltage stays lower than the specific voltage determined for a SRAM core. This voltage is also found to be comparable but slightly smaller than the static voltage margin of SRAM cells. In-place measurements using the extended DPI provide an in-depth understanding of the susceptibility and help us to enhance the immunity of VLSI circuits.

Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector

Built-in self-test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to perform radio-frequency signal analysis. Existing on-chip resources, such as power or envelope detectors or small additional circuitry, can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as in-phase and quadrature (IQ) imbalance, and third-order intermodulation intercept point (IIP3) is challenging. Since IQ imbalances are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a multistep BiST technique for transmitter IQ imbalance and nonlinearity using a self-mixing envelope detector. We derive analytical expressions for the output signal in linear and nonlinear modes. Using linear mode expression, we devise test signals to isolate the effects of gain and phase imbalances, dc offsets, and time skews from other parameters of the system in low-power mode. Once isolated, these parameters are calculated easily with a few mathematical operations. In the next step, using a higher power test signal, the nonlinear behavior of the transmitter is excited and the IIP3 of the transmitter is computed based on the analytical expressions. Simulations and hardware measurements show that the technique can provide accurate characterization of the path.

Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique

This brief describes a built-in self-test (BIST) technique used to verify and tune the timing integrity of a clock distribution system implemented with injection-locked rotary traveling-wave oscillators (RTWOs). The die is fabricated in a 130-nm CMOS process and occupies 4.4 mm $\times$ 2.25 mm and is limited by the outer diameter of the RTWOs, leaving internal space for other circuits. The BIST circuits take a chip area of only 0.025 $\hbox{mm}^{2}$ . The measured frequency tuning range of the RTWOs is from 1.7 to 2.0 GHz. The measured RTWO phase tuning range is 58.56 $^{\circ}$ with a worst case 0.34 $^{\circ}$ phase tuning resolution. The injection-locked clock multiplication and distribution network achieves a single-sideband integrated RMS jitter of 66.8 fs from 10-kHz to 40-MHz offset frequencies at 2.04-GHz output. The BIST circuit allows testing of the integrity of the clock distribution system at speed by determining if the system clock skew can be tolerated or needs adjustment. To the authors' knowledge, the implementation of this BIST technique to determine clock integrity of an injection-locked clock distribution network has not been explored previously.