Performance Analysis of BIST Algorithms

Abstract

Objective: Performance analyses of March LR and March C- are presented to achieve high fault coverage, low power dissipation, less area utilization and minimum testing time. Methods: Testing of memory consist of Built-In-Self-Test (BIST) controller and circuit-under-test. BIST algorithms are resided inside the BIST controller. BIST algorithms such as March LR and March C- are coded in term of finite state machine. Memory is modeled in verilog and simulated in ModelSims for testing memory faults and it is synthesized by using Xilinx Vivado 2012.2 EDA tool for power, area and timing analysis. Findings: Memory tests are conducted to verify the correctness of each memory location. It involves writing a particular set of data to each memory location and checking that data by reading it. After reading back, if the values are same as those of writing values, then the test is past. If not, the test is fail. Various test methodologies have been developed to detect the memory defects. One such test is BIST technique. Before implementing BIST algorithm, it is necessary to study the various functional faults models for memory defects. The commonly occurs faults are Stuck-At Fault (SAF), Stuck Open Fault (SOF), Transition Fault (TF), Coupling Fault (CF) etc. These functional faults are model and write the code in verilog. Faults are inserted and detected using ModelSims. Using Xilinx Vivado 2012.2 EDA tool, power, area and timing are analyzed. Comparison is made between March C- and march LR. Even though March LR has more length (14N), it has high fault coverage and lesser power dissipation. Thus, March LR is more efficient than March C-. Applications/Improvements: The fault coverage is improved by using March LR. More improvement in March LR can detect more faults which result in the efficiency for online BIST. Keywords: BIST Algorithm, Built-In-Self-Test (BIST), March C- and March LR, Memory Testing