Performance Analysis of March M & B Algorithms for Memory Built-In Self-Test (BIST)

Abstract

It has been acknowledged that for the chips designed at the deep sub-micron (DSM) level, the on-chip memory part is covering the maximum area of the integrated circuits. It is recommended to provide the testing mechanism in the IC design at higher abstraction levels to optimize the time, effort, and money. Therefore, memory testing is an essential characteristic of the chip design and strategy. The memory test model comprises a memory test algorithm for a build in self-test controller. The BIST controller utilizes the various functional blocks to test the memory by marching through in a specific order of sequential test elements. This paper represents the comparative performance analysis of March-B and March-M memory test algorithms with help of a memory BIST controller. The march-based testing detects memory structural faults at functional levels. In this case study, a testing architecture for a memory size of8-bit data with a depth of28. The designed model makes use of the March-M algorithm and provides the fault coverage for the functional fault models such as stuck-at fault, transition fault, and coupling fault using different logical operations performed between March-M elements. However, in the case of the March-B algorithm, it provides coverage of stuck-at transition fault only. It is observed that extra sequences of elements ate required for coverage of coupling fault. Thus, it is suggested to use the March-M test algorithm for memory tests to detect the maximum fault and achieve high fault coverage. This architecture is described in VHDL hardware description language (HDL) and simulated using Xilinx Vivado tool [2018}.