Abstract
A memory test algorithm for detecting neighborhood pattern sensitive faults (NPSFs), including static NPSF (SNPSF), passive NPSF (PNPSF) and active NPSF (ANPSF), is proposed in this paper. The patterns can also detect all the traditional faults present in the memory array such as stuck-at faults (SAFs), transition faults (TFs), coupling faults (CFs) and address decoder faults. Next, a built-in self-test (BIST) architecture is proposed with low area overhead. The test pattern generator (TPG) for generating all patterns for NPSFs is implemented with on-chip cellular automata (CA) based circuit.
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