Built-in Self-test Scheme Research Articles

An Accumulator-Based Compaction Scheme For Online BIST of RAMs

Transparent built-in self test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional transparent BIST schemes, achieving considerable reduction in test time. In symmetric transparent BIST schemes proposed to date, output data compaction is performed using either single-input or multiple-input shift registers whose characteristic polynomials are modified during testing. In this paper the utilization of accumulator modules for output data compaction in symmetric transparent BIST for RAMs is proposed. It is shown that in this way the hardware overhead, the complexity of the controller, and the aliasing probability are considerably reduced.

Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs

Linear finite-state machines (LFSMs) such as linear feedback shift registers (LFSRs), cellular automata (CA), and ring generators (RGs) are used as test pattern generators in built-in self-test schemes that employ 2-D scan design. These mechanisms are usually accompanied by phase shifters (PSs) in order to avoid the degradation of the fault coverage caused by correlations/dependences in the produced test bit sequences. Given this context, we investigate in this paper the potential of generalized (or Galois) LFSRs (GLFSRs) as onboard test pattern generators. We compare GLFSRs with and without PSs against LFSMs with PSs (LFSM/PSs) for various types of LFSMs (LFSRs, CA, RGs, and dense RGs) on two accounts: channel separation and overall hardware cost. Experimental results show that GLFSRs achieve larger channel separation with lower hardware cost than LFSM/PS and attain higher fault coverage.

An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

SCT

Novel strategies are necessary to efficiently test and configure emerging reconfigurable nanoscale devices, in addition to providing defect tolerance. This is mainly due to the high defect densities that are expected for these devices. Among different approaches, reconfiguration-based defect avoidance has proven to be a practical solution. However, configuration time, test time, and defect-map size remain among the major challenges for these new devices. In this article, we propose a new approach (called SCT) that simultaneously performs test and configuration. The proposed method uses a built-in self-test (BIST) scheme for test and defect tolerance. The method is based on testing reconfigurable nanoblocks at the time of implementing a function of a desired application on that block. The SCT method considerably reduces the total test and configuration time. It also eliminates the need for storing the location of defects in a defect map on- or off-chip. The presented probabilistic analysis results show the effectiveness of this method in terms of test and configuration time for architectures with rich interconnect resources. Also, a Verilog simulation model is developed for crossbar-based nano-architectures. This model is used to implement several MCNC benchmarks based on the proposed SCT method. The simulation results demonstrate efficiency of the method in terms of test time and yield under different defect rates.

Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.

A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences

Test set embedding built-in self test (BIST) schemes are a class of pseudorandom BIST techniques where the test set is embedded into the sequence generated by the BIST pattern generator, and they displace common pseudorandom schemes in cases where reverse-order simulation cannot be applied. Single-seed embedding schemes embed the test set into a single sequence and demand extremely small hardware overhead since no additional control or memory to reconfigure the test pattern generator is required. The challenge in this class of schemes is to choose the best pattern generator among various candidate configurations. This, in turn, calls for a need to evaluate the location of each test pattern in the sequence as fast as possible, in order to try as many candidate configurations as possible for the test pattern generator. This problem is known as the test vector-embedding problem. In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(1). The applicability of the presented method for embedding test sets for the testing of real-world circuits is investigated through experimental results in some well-known benchmarks; comparisons with previously proposed schemes indicate that comparable test lengths are achieved, while the time required for the calculations is accelerated by more than 30 times.

An ALU-Based BIST Scheme for Word-Organized RAMs

Testing of word-organized memories has been performed in one of these three ways: (1) by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intraword fault model), (2) by applying special tests to target intraword faults in addition to applying tests for bit-organized memories, or (3) by applying march tests bit-by-bit to the memory words. The latter solution results in decreased hardware overhead. In this paper, a novel Built-in Self-Test (BIST) scheme is proposed to serially apply march tests bit-by-bit to word-organized RAMs, utilizing an ALU whose inputs are driven by a barrel shifter. Comparisons with schemes that have been proposed in the open literature for the same purpose reveal that the proposed scheme achieves the same fault coverage within the same or lower time and with lower area overhead. More precisely, an overhead of n + 3 gates is required for the application of the required patterns to the RAM inputs and the evaluation of the corresponding outputs, as opposed to the 8n or 11n gates required by schemes proposed previously.

An Introduction to Logic Circuit Testing

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. Table of Contents: Introduction / Fault Detection in Logic Circuits / Design for Testability / Built-in Self-Test / References

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With $-$75 dBc Single-Tone Sensitivity at 100 kHz Offset

An on-chip clock phase-noise measurement circuit is presented. Unlike previously reported monolithic measurement techniques that measure jitter in the time domain, the proposed module measures the phase-noise spectrum. The proposed circuit is fully integrated and does not require a spectrally clean reference clock or any external calibration. The module can be integrated as part of a built-in self-test (BIST) scheme for PLL clock synthesizers. The proposed circuit uses a low-noise voltage-controlled delay-line (VCDL) and mixer-based frequency discriminator to extract the phase-noise fluctuations at baseband. A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point. The proposed circuit is fabricated using a 0.25 mum digital CMOS process and operates up to a 2 GHz carrier frequency. It achieves a single-tone measurement sensitivity of -75 dBc and an equivalent phase-noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.

An ADC BIST with on-chip ramp generator

This work presents built-in self-test (BIST) techniques for the production testing of mixed signal circuits. The special test strategy for the typical mixed-signal component analog-to-digital converter (ADC) is discussed. The traditional test for such mixed-signal components can be completed through a DSP-based mixed-signal tester with an arbitrary waveform generator and a signal digitizer, but such a test is very costly and time consuming. Hence, a BIST strategy based on an on chip ramp generator (OCRG) is proposed in this work for testing ADC. This BIST method has an advantage testing ADC without DAC to overcome area overhead. This BIST method realizes the test controller, test pattern generation and output response analyser at the aspect of the on-chip circuitry. The demonstration of the proposed BIST is given through various simulation results in the last parts of this work.

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

Pseudofunctional testing

Recent research results have shown that the traditional structural testing for delay and signal integrity faults may result in overtesting due to the nontrivial number of such faults that are untestable in the functional mode although testable in the test mode. This paper presents a pseudofunctional-test methodology that attempts to minimize the overtesting problem of the scan-based circuits in automatic test pattern generation (ATPG) and built-in self-test (BIST) test generation approaches. The first pattern of a two-pattern test is still delivered by scan in the test mode but the pattern is generated in such a way that it does not violate the functional constraints extracted from the functional logic. The second pattern is then generated in a functional mode using the functional justification (also called broadside) test application scheme. The authors use a sequential boolean satisfiability solver to extract a set of functional constraints that consists of illegal states and internal signal correlation. The functional constraints are imposed upon an ATPG tool to generate pseudofunctional tests and/or implemented as a monitor in the BIST environment to allow only functional-like patterns generated from the random test pattern generator as tests. The experimental results for delay faults indicate that the percentage of functionally untestable delay faults is nontrivial for many circuits. This finding supports the hypothesis of the overtesting problem in delay testing. In addition, the results indicate the effectiveness of the proposed constraint extraction method and the proposed BIST scheme.

A Stability Criterion for High-Accuracy<tex>$Delta$</tex>–<tex>$Sigma$</tex>Digital Resonators

While microelectronic companies are increasingly focused on the production of system on chips (SoCs) comprising both analog and digital sections, the expenses related to the test of high-density mixed-signal chips have become the main cost factor due to the long testing time and the need for complex automated test equipment (ATE). Built-in self-test (BIST) techniques represent an effective solution to tackle this problem, as they rely on the integration of testing-oriented resources on the same chip to be tested. Among all the possible circuits to be used for BIST purposes, simple and high-purity harmonic resonators are essential to perform an accurate characterization of analog-to-digital converters (ADCs). In particular, /spl Delta/-/spl Sigma/ harmonic resonators are very suitable for BIST schemes, but they have proved to be critically stable and difficult to implement due to the lack of clear design criteria. In this paper, a general method to analyze the behavior of /spl Delta/-/spl Sigma/ harmonic resonators is presented. The proposed criterion suggests some guidelines to implement more stable and robust resonators.

Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit

This paper presents a new low-cost RF BIST (Built-In Self-Test) scheme that is capable of measuring input impedance, gain, noise figure and input return loss for a low noise amplifier (LNA) in RF systems. The RF BIST technique requires an additional RF amplifier and two peak detectors, and its output is a DC voltage level. The BIST circuit is designed using 0.18 µm SiGe technology. The test technique utilizes output DC voltage measurements and these measured values are translated into the LNA specifications such as input impedance and gain using the developed mathematical equations. Simulation results are presented for an LNA working at 5 GHz. Measurement data are compared with simulation results to validate the developed mathematical equations. The technique is simple and inexpensive.

A Dual-Mode Built-in Self-Test Technique for Capacitive MEMS Devices

A dual-mode built-in self-test (BIST) scheme which partitions the fixed (instead of movable) capacitance plates of a capacitive microelectromechanical system (MEMS) device is proposed. The BIST technique divides the fixed capacitance plate(s) at each side of the movable microstructure into three portions: one for electrostatic activation and the other two equal portions for capacitance sensing. Due to such a partitioning method, the BIST technique can be applied to surface- and bulk-micromachined MEMS devices and other technologies. Further, the sensitivity and symmetry dual BIST modes based on this partitioning can also be developed. The combination of both BIST modes covers a larger defect set, so a more robust testing result for the device can be expected. The BIST technique is verified by three typical capacitive MEMS devices. Simulation results show that the proposed technique is an effective BIST solution for various capacitive MEMS devices.

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24db and bandwidth of 3.9GHz.

Improving test effectiveness of scan-based BIST by scan chain partitioning

Test effectiveness of a test-per-scan built-in self-test (BIST) scheme is highly dependent on the length and number of scan chains. Fewer cycles are used to capture test responses when the length of the scan chains increases and the total number of clock cycles is fixed. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-flops are not observable during the shift cycles. A new scan architecture is proposed to make a scan-based circuit more observable. The scan chain is partitioned into multiple segments. Multiple capture cycles are inserted to receive test responses during the shift cycles compared to the test-per-scan test scheme. Unlike other BIST schemes using multiple capture cycles after the shift cycles, our method inserts multiple capture cycles inside the shift cycles, but not after the shift cycles. Unlike the previous method that drives multiple scan segments by a single scan-in signal, the proposed method uses a new architecture to control all scan segments by different signals. Sufficient experimental results are presented to demonstrate the effectiveness of the method.

Embedded Test Control Schemes Using iBIST for SOCs

This paper presents novel control schemes for testing embedded cores in a system-on-a-chip. It converts a traditional built-in self-test (BIST) scheme into an externally controllable scheme to achieve high test quality within optimal test execution time without inserting test points. Interactive BIST promotes design and test reuse without revealing IP information by using a pattern matching technique instead of fault simulation.

A Low-Cost Concurrent BIST Scheme for Increased Dependability

Built-in self-test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed concurrent test latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to concurrent test latency and hardware overhead trade-off, for low values of the hardware overhead.