Abstract
Test set embedding built-in self test (BIST) schemes are a class of pseudorandom BIST techniques where the test set is embedded into the sequence generated by the BIST pattern generator, and they displace common pseudorandom schemes in cases where reverse-order simulation cannot be applied. Single-seed embedding schemes embed the test set into a single sequence and demand extremely small hardware overhead since no additional control or memory to reconfigure the test pattern generator is required. The challenge in this class of schemes is to choose the best pattern generator among various candidate configurations. This, in turn, calls for a need to evaluate the location of each test pattern in the sequence as fast as possible, in order to try as many candidate configurations as possible for the test pattern generator. This problem is known as the test vector-embedding problem. In this paper we present a novel solution to the test vector-embedding problem for sequences generated by accumulators. The time overhead of the solution is of the order O(1). The applicability of the presented method for embedding test sets for the testing of real-world circuits is investigated through experimental results in some well-known benchmarks; comparisons with previously proposed schemes indicate that comparable test lengths are achieved, while the time required for the calculations is accelerated by more than 30 times.
Highlights
The problem of testing VLSI chips is becoming more and more time- and memory-consuming
For the testing of the chips fabricated today, complicated testing scenarios are applied, which incorporate both external testers and on-chip resources. The latter fall into the category of built-in self-test (BIST) techniques that provide for test pattern generation and response verification operations on chip [1]
In pseudorandom BIST schemes [2], either synthesizable modules or modules that already exist into VLSI chips are utilized for the generation of test patterns
Summary
The problem of testing VLSI chips is becoming more and more time- and memory-consuming. A precomputed (deterministic) test set is embedded into a sequence generated by a pseudorandom generator In this way, the number of the applied pseudorandom patterns is decreased, without affecting the hardware or the impact on the timing parameters; such schemes apply when reverse-order simulation [7] cannot be applied. In certain low-budget applications, the BIST hardware overhead needs to be as simple as possible In these cases, singleseed solutions, where the test pattern generator is initialized and left to operate for a predetermined number of cycles until all faults under question are detected, may be a preferable solution. The hardware overhead of single-seed accumulatorbased BIST schemes is extremely low, since the need for storage is eliminated; for example, the module presented in Figure 1 can be configured in such way that the inputs of the accumulator are driven by the outputs of a register of the register file.
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