A Low-Cost Concurrent BIST Scheme for Increased Dependability

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in on-line and in off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel concurrent BIST scheme is presented, termed Square Windows Monitoring (SWiM) concurrent BIST, which is based on monitoring input vectors using a square window; it is shown that SWiM is superior to previously proposed input vector monitoring schemes, with respect to concurrent test latency and hardware overhead trade-off.

Built-In Self-Test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Among the BIST techniques the Comparative Concurrent BIST (C-BIST) has various advantages since it provides for off-line test generation, when it is desirable, and thus accomplishes a mixed on-line/off-line BIST scheme. However, in C-BIST when the test sequence is long, the time required for all the test vectors to appear among the normal inputs to the circuit (test latency) is significantly long. Modifications of the C-BIST technique have been proposed in order to reduce the test latency. In this paper we propose a new C-BIST technique termed windowed-CBIST (w-CBIST) for test latency reduction. The proposed technique is shown to be significantly more efficient from the previous methods with respect to test latency and hardware overhead.

As SOC and complex systems usually include analogue IPs, it becomes more important to test analogue devices efficiently. The reason for this is that analogue testing for high quality requires substantial testing costs although the analogue portion in a whole chip or in a system is usually very small. In the paper, an efficient low-cost built-in self-test (BIST) scheme is developed for testing A/D converters. The key ideas are to use a triangular wave as a test input signal and to analyse the output response for functional testing. In order to perform functional testing, new fault models called successive value, oscillation and bit faults are proposed. Testing these faults guarantees the quality of A/D converters. For experimental results, a D-S A/D converter and a pipeline A/D converter are used. The results show that the new BIST scheme is very efficient in terms of fault coverage and hardware overhead. the presence of pre-existing DSP capabilities and the presence of both an A/D converter and a D/A converter. Another BIST approach uses pulse response sampling (4). This BIST uses pulse trains of varying duty ratio, generated from a digital linear feedback shift register (LFSR), as a test stimulus. The responses of the device under test (DUT) are sampled and compared with reference voltages to generate binary sequences that can be compressed to yield a signature for the anticipated responses. The BIST scheme using pulse response sampling has the advantage of a very small hardware overhead, but it takes a long time to test in high fault conditions. Finally, the BIST architecture, which is most widely known, is a histogram-based analogue BIST architecture (5-7). This method is based on statistical analysis of the A/D converter output code. In this approach, an analogue signal is applied to the A/D converter input and the number of times each code appears on the A/D converter output is recorded. These recorded samples are compared with theoretical values and then the BIST makes a decision whether the A/D converter is fault- free or faulty. To store both the measured and ideal histograms, the histogram test technique requires a large amount of hardware resources both in terms of memory and operative resources. In addition, a large number of samples and several successive periods of the signal are required to achieve satisfactory results. This paper investigates the viability of a new BIST approach. The input test signal waveform of A/D converters is a triangular wave obtained from an integrator. Then the output of the A/D converters is compared with the reference voltages, which are related to the three defined fault models used by the BIST. The proposed scheme is applicable to any A/D converter because it is related to functional testing. Comparing this new BIST with other BIST, this scheme does not need any DSP resources. Moreover, the proposed BIST has a small hardware overhead but achieves high fault coverage. Just three periods of input signal are required to achieve high fault coverage, so test time is reduced. 2 New test methodology

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: off-line and on-line. Input vector monitoring concurrent BIST schemes are a class of on-line techniques that circumvent the problems appearing separately in on-line and in off-line BIST. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic off-line and concurrent online. The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper a novel input vector monitoring concurrent BIST scheme based on a pre-computed test set is presented. The proposed scheme can perform both concurrent on-line and off-line testing; therefore it can be equally well utilized for manufacturing and concurrent on-line testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a pre-computed test set that can perform both concurrent on line and off-line testing.

This paper presents a Built-In Self-Test (BIST) technique to test the setup and hold times of memory interface circuitry. The BIST scheme generates data and clock using an on-chip pattern generator. The relative timing difference between data and clock is controlled using a cycle-by-cycle control method for testing. Two test methods of static and dynamic modes have been presented to measure the timing difference and then are used to specify the setup and hold times. The static mode is mainly used to detect pass or fail for timing specifications, and the dynamic mode is devised to measure the amount of timing mismatches and thus detect timing margin degradations due to the timing delay mismatches. Using these two test modes, the BIST scheme obtains test results with low frequency signals, which are compatible with low performance testers. The test chip including the BIST scheme has been fabricated with a commercial 0.18-μm CMOS process. The chip measurement results are shown to validate the testability of the BIST scheme for the setup and hold times of memory devices.

Input vector monitoring concurrent Built-In Self-Test (BIST) schemes can circumvent problems appearing separately in on-line and off-line BIST techniques. The concurrent test latency of an input vector monitoring concurrent BIST scheme is the time required in order to complete the concurrent test. In this paper a novel input vector monitoring concurrent BIST scheme is presented. The proposed BIST scheme is shown to have lower hardware overhead for the same values of the concurrent test latency compared to previously proposed schemes.

An original BIST (built-in self-test) scheme is proposed to cover some shortcomings of self-checking circuits and to ensure all tests needed for integrated circuits. In the BIST scheme, self-checking techniques and built-in self-test techniques are combined in an original way and take advantage one from the other. This results in a unified BIST scheme (UBIST), allowing a high fault coverage for all tests needed for integrated circuits, e.g. offline test (design verification, manufacturing test, and maintenance test) and online concurrent error detection. >

A low power test-per-clock built-in self-test (BIST) scheme based on 2-bit TRC is presented in this paper. The low power during testing can be obtained by selectively activating multi 2-bit twisting ring counters (AM2B-TRC). The optimal number of activated 2-bit twisting ring counters is also explored in this paper. Experimental results based on ISCAS'85 benchmark circuits show that the proposed low power test-per-clock BIST scheme has the improved performance including power, fault coverage and test length, comparing with the corresponding already known low power test-per-clock BIST scheme. In addition, the advantage of the proposed low power test-per-clock BIST scheme can be used for testing more than one module in a system on a chip (SoC).

Manufacturing test is carried-out once to ensure the correct operation of the circuit under test right after fabrication, while testing is carried-out periodically to ensure that the circuit under test continues to operate correctly on the field. The use of offline built-in self-test (BIST) techniques for periodic testing imposes the interruption of the normal operation of the circuit under test. On the other hand, the use of input vector monitoring concurrent BIST techniques for periodic testing provides the capability to perform the test, while the circuit under test continues to operate normally. In this paper, a novel input-vector monitoring concurrent BIST technique for combinational circuits based on a self-testing RAM, termed R-CBIST, is presented. The presented technique compares favorably to the other input vector monitoring concurrent BIST techniques proposed so far with respect to the hardware overhead, and the time required for the concurrent test to be completed (concurrent test latency). R-CBIST can be utilized to test ROM because it results in small hardware overhead, whereas there is no need to stop the ROM normal operation.

This paper presents a Built In Self Test (BIST) scheme for very high parallelism memory testing to be done on a BIST Board with DC stimuli. A BIST scheme with ten algorithms was implemented on a 256Meg, 4 banks, X32 SDRAM. Self Test operation is synchronized by an on chip oscillator which also generates internal timing signals needed for memory testing. Various ways to test the functionality of BIST circuitry as well as some engineering and debug features are also included.

Phase Locked Loops (PLLs) are required to meet analog specifications such as lock time, phase error, jitter in addition to the frequency lock test in production. Parametric testing of PLLs is resource intensive and requires high precision hardware on the Automatic Test Equipment (ATE). This paper proposes a Built in Self Test (BIST) scheme to perform functional and parametric testing using low frequency ATE resources. The BIST module is independent of the PLL frequency and can be used effectively in multi-PLL System-on-a-Chip (SoC) modules. The scheme uses the Phase Detector (PD) output signature to test for lock and transient response using a digital BIST module. The BIST scheme is designed without impacting the mission mode performance by not perturbing analog nodes and the phase sensitive feedback loop. The test methodology enables parametric testing for process variation and specification compliance while using minimal external test resources. Process and operating condition independence is a critical factor to ensure compatibility with volume manufacturing and test environments.

Embedded memory plays an important role in modern system-on-chip designs. However, the reliability issue of embedded memories becomes more and more critical with the shrinking of transistor feature size. This paper proposes a programmable online/off-line built-in self-test (BIST) scheme for random access memories (RAMs) with error correction code (ECC). The BIST scheme can be used for performing production testing and periodic transparent testing. In comparison with an existing transparent BIST scheme, the proposed BIST scheme does not incur the aliasing problem. Also, it can provide good fault location capability in online test mode. Experimental results show that the area cost of the proposed online/off-line BIST scheme is low—only about 2.6% for a 4K×39-bit SRAM.

Effective built-in self-test (BIST) schemes using deterministic sequences generated by small counters have been proposed in the past for the common multiplier/accumulator pair. In this paper we show how near complete testability can be achieved with a regular counter-generated deterministic test set for the shifter-accumulator pair (accumulation performed either by an adder or an ALU) which appears very often in embedded processor or DSP datapaths. The BIST scheme provides near complete coverage with respect to the stuck-at fault model for any datapath width as it is verified by a comprehensive set of experiments. The proposed BIST scheme uses the same test pattern generation (counters) and output data evaluation (accumulators) resources as in our earlier BIST schemes for multiplier/accumulator pairs, thus completing a deterministic counter-based datapath BIST architecture.

A novel design is exhibited in the paper presented here for an analog-to-digital converter (ADC) built-in self test (BIST) scheme using code-width technique. An 8-bit sigma-delta ADC BIST scheme is introduced. The 8 bit sigma-delta ADC with arbitrary faults is simulated in the given BIST scheme designed in CMOS 45nm technology. Different parametric faults have been detected here such as Differential Non Linearity (DNL), monotonicity fault and missing code fault. This architecture of ADC BIST is achieved by Tanner EDA tool v15.0 using 45nm BSIM4 CMOS technology. The power dissipation of the BIST circuit is 18mW for the power supply of 1V.

The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.