Buffer Circuit Research Articles

Design of Superlattice Ferroelectric-Metal Field-effect Transistor for triple-level cell 3D NAND flash

Superlattice ferroelectric-metal field-effect transistor (SL-FeMFET) based three-dimensional NAND architecture (3D NAND) is investigated for triple-level cell (TLC) operations. The SL-FeMFET shows a novel approach for designing the gate-stack using a superlattice of ferroelectric/dielectric/ferroelectric for achieving large memory window ∼3.48 V with program/erase voltage ±7 V for 3D NAND architecture. By TCAD modeling, we demonstrate TLC operation of SL-FeMFET with improving memory window and alleviating variability caused by floating metal layer in FeMFET structure. In addition, as the vertical gate stack increases from 256-layer to 512-layer, the read-out current with worst cases in seven read operations for TLC sensing are examined using page buffer circuit for sensing operation. The simulation results suggest that SL-FeMFET based 3D NAND architecture can operate 512-layer with sufficient sense margin for TLC operation.

INDIDO: A novel low-power approach for domino logic circuits

Power dissipation in Nanoelectronic circuits at advanced technology nodes is dominated by leakage power dissipation. This is due to an increase in short channel effects in the scaled transistors.The VLSI industry is seeking alternative options to enhance the performance of portable electronic systems by ensuring higher speed and reduced power dissipation. In the ultra-deep submicron (DSM) regime, a new device called the fin-shaped field effect transistor (FinFET) was developed to replace CMOS technology. FinFET, a multi-gate device, significantly reduces power dissipation compared to planer MOS (Metal Oxide Semiconductor ) transistor, but it doesn’t entirely resolve the issue. To further reduce power dissipation in the ultra DSM regime, low power approaches are required. Domino logic, a widely-used dynamic logic, is commonly utilized in high-speed VLSI architectures. In this research work, a novel INput Dependent Inverter DOmino (INDIDO) logic approach for low-power domino logic circuits using FinFET devices is proposed. A comparative analysis between the proposed INDIDO method and the existing approaches is performed for domino logic circuits for various performance metrics at the 16 nm technology node. In this research, various circuits like domino buffer, domino OR, domino AND, domino XOR and domino half adder are designed using the proposed INDIDO approach.The proposed INDIDO FinFET buffer circuit offers significant improvement in energy efficiency and FOM (Figure of Merit) by 53.18% and 82% respectively as compared to conventional FinFET footed domino buffer circuit. Beside this, proposed circuits like INDIDO OR, INDIDO AND, INDIDO XOR and INDIDO Half adder circuit follow the same trend as INDIDO buffer circuit and show better performance parametres in comparison to the existing low power domino approaches as well. In addition to this, the proposed INDIDO buffer circuits are also analyzed for PVT(process voltage and temperature) variability.This whole analysis makes us to conclude that proposed INDIDO approach reduces power dissipation and delay penalty, have high noise tolerance capacity, more immunity against PVT variations and high energy efficiency in comparison to the already existing techniques.

An Improved Bi-Switch Flyback Converter with Loss Analysis for Active Cell Balancing of the Lithium-Ion Battery String

This paper focuses on the active cell balancing of lithium-ion battery packs. An improved single-input, multioutput, bi-switch flyback converter was proposed to achieve effective balancing. The proposed topology simplifies the control logic by utilising a single MOSFET switch for energy transfer and two complementary pulses to control the cell-selecting switches. The proposed topology can decrease the number of switching devices as well as the size and cost of the system. The bi-switch flyback converter eliminates the need for a separate buffer circuit to minimise leakage and electromagnetic inductance. Losses and energy efficiency were analysed at each end of the proposed topology. The appropriate MATLAB simulations investigated the balancing characteristics of various state of charge (SOC) imbalances. A comparison is made between the balancing speed and energy transfer efficiency of the proposed topology and a conventional topology that employs a multi-input and multi-output flyback converter in a static mode. The results of the MATLAB simulation were validated by the OPAL-RT (OP5700) real-time simulator. The balancing data of the proposed topology were compared using MATLAB simulation and real-time simulation. This work may reduce the time required to assemble and commission the hardware for the proposed topology’s real-time implementation.

CC-CBTA-Based Floating Inductance Simulator with CM/VM PID Controllers

This work describes voltage-mode (VM), current-mode (CM) PID controllers and an electrically controllable floating inductance (FI) simulator circuit. Only a single current-controlled current backward transconductance amplifier (CC-CBTA) and a grounded capacitor are used in the proposed FI simulator circuit. One CBTA, one CC-CBTA, two capacitors and one resistor are used in the proposed PID controllers. All of the proposed circuits have appropriate input and output impedance values, allowing them to be utilized in cascade connections without requiring a buffer circuit. There is also no matching constraint between the active and passive values of the proposed circuit. The SPICE software environment and experimental results were used to validate theoretical derivations and associated outcomes. The layout of the CC-CBTA has been built, and the post-layout simulations are carried out using the netlist extracted from the layout. Comparisons were made with similar circuits found in the professional literature.

500 MS/s 4-Bit Flash ADC with Complementary Architecture

This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 V<sub>pp</sub> operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm<sup>2</sup> and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz.

Design, Fabrication, and Characterization of a PTAT Sensor Using CMOS Technology

This paper presents the design of an integrated temperature sensor. The sensor was manufactured using the 3 µm CMOS technology. The proportional to absolute temperature sensor output signal was produced by two MOS transistors with biasing and buffering circuits. The sensor output voltage was linearly proportional to the absolute temperature in a wide range of temperature values. The measurement results coincide very well with the results of the process corner analysis. Certain non-linearities occurring at high temperature values are investigated in this paper in more detail. Additionally, the influence of neighboring circuits present in the manufactured integrated circuit on the sensor temperature response is studied.

Current-mode PID controllers employing commercially available active components

This work describes two current-mode (CM) PID controllers using only two commercially active components, namely, current feedback operational amplifier (CFOA), and four passive components, i.e. two capacitors and two resistors. They have appropriate output and input impedance values, allowing them to be utilized in cascade connections without requiring a buffer circuit. Since all capacitors are grounded, it is suitable for integrated circuit (IC) technology. Moreover, the controllers can be easily modified to operate in voltage-mode (VM), transimpedance-mode (TIM), and transadmittance-mode (TAM) PID controllers. Using 0.18 µm CMOS parameters and the PSPICE program, the proposed circuits are simulated to verify the theoretical behavior. To demonstrate the viability of the circuits, experimental tests using commercially available AD844 integrated circuits are performed. The suggested PID circuits are alsoexperimental tested in a closed-loop system as an example.

0.5-V 281-nW Versatile Mixed-Mode Filter Using Multiple-Input/Output Differential Difference Transconductance Amplifiers.

This paper presents a new low-voltage versatile mixed-mode filter which uses a multiple-input/output differential difference transconductance amplifier (MIMO-DDTA). The multiple-input of the DDTA is realized using a multiple-input bulk-driven MOS transistor (MI-BD-MOST) technique to maintain a single differential pair, thereby achieving simple structure with minimal power consumption. In a single topology, the proposed filter can provide five standard filtering functions (low-pass, high-pass, band-pass, band-stop, and all-pass) in four modes: voltage (VM), current (CM), transadmittance (TAM), and transimpedance (TIM). This provides the full capability of a mixed-mode filter (i.e., twenty filter functions). Moreover, the VM filter offers high-input and low-output impedances and the CM filter offers high-output impedance; therefore, no buffer circuit is needed. The natural frequency of all filtering functions can be electronically controlled by a setting current. The voltage supply is 0.5 V and for a 4 nA setting current, the power consumption of the filter was 281 nW. The filter is suitable for low-frequency biomedical and sensor applications that require extremely low supply voltages and nano-watt power consumption. For the VM low-pass filter, the dynamic range was 58.23 dB @ 1% total harmonic distortion. The proposed filter was designed and simulated in the Cadence Virtuoso System Design Platform using the 0.18 µm TSMC CMOS technology.

A fully balanced first order high-pass filter

The topic of this article is the design of a fully balanced first-order high-pass filter and its two circuits. The first circuit is a fully balanced current-tunability first-order high-pass filter consisting of four NPN transistors and a single capacitor, which is a simple design and quite compact. The pole frequency can be adjusted with a bias current. The results of the first circuit shows the phase and gain responses, the phase and gain responses when adjusted with a bias current, the time-domain response, and the harmonic spectrum. However, this circuit found a flaw in the temperature that affects the pole frequency, and total harmonic distortion is relatively high. Therefore, the second circuit improves defects by the CAPRIO technique to reduce the total harmonic distortion, and the resistors in the circuit are added to the design to replace the resistance and the effect of temperature on the properties of the transistor. This circuit consists of four NPN transistors, four resistors, and a single capacitor. The resistors in this circuit can be adjusted to change the pole frequency and voltage gain. The results of the second circuit show the gain and phase responses of the proposed circuits, the phase and gain responses when adjusted to the value of the resistor, the phase and gain responses at various temperatures, as well as their time-domain responses and total harmonic signal distortion. The all-pass filter is also made using the filter introduced in the second circuit because of its voltage gain-adjustable property. So, if the suggested circuit is constructed in combination with a buffer circuit to make it feasible to function as an all-pass filter, the result will be an all-pass filter. In accordance with the results of this study, we have introduced a design for a high-pass filter to reduce total harmonic distortion and the effect of temperature

Passive Impedance-Matched Neural Recording Systems for Improved Signal Sensitivity.

Wireless passive neural recording systems integrate sensory electrophysiological interfaces with a backscattering-based telemetry system. Despite the circuit simplicity and miniaturization with this topology, the high electrode-tissue impedance creates a major barrier to achieving high signal sensitivity and low telemetry power. In this paper, buffered impedance is utilized to address this limitation. The resulting passive telemetry-based wireless neural recording is implemented with thin flexible packages. Thus, the paper reports neural recording implants and integrator systems with three improved features: (1) passive high impedance matching with a simple buffer circuit, (2) a bypass capacitor to route the high frequency and improve mixer performance, and (3) system packaging with an integrated, flexible, biocompatible patch to capture the neural signal. The patch consists of a U-slot dual-band patch antenna that receives the transmitted power from the interrogator and backscatters the modulated carrier power at a different frequency. When the incoming power was 5-10 dBm, the neurosensor could communicate with the interrogator at a maximum distance of 5 cm. A biosignal as low as 80 µV peak was detected at the receiver.

Skin Detection System Using Infrared Optoelectronic Technology and Its Application in Facial Recognition

Facial recognition technology has made significant progress. However, variable lighting conditions can affect its performance. Considering the need to scan facial skin for recognition purposes, this study proposes a miniature optoelectronic acquisition system for skin in the near-infrared range. The system utilizes the C11708MA photodetector from Hamamatsu Photonics’ MS series as the probe for spectral data acquisition. Other hardware components are designed accordingly. A three-stage amplification buffer circuit is employed as the front-end acquisition and preprocessing circuit. The AD7671 chip from Analog Devices Inc. is selected as the AD converter, and the communication module utilizes the CY7C68013 chip from Cypress’ EZ-USB FX2 series. The control and transmission module employs the EP2C5T144C8N FPGA chip from ALTERA’s Cyclone II generation. In order to address the power supply requirements of the CY7C68013 USB chip (3.3 V), the FPGA core (1.2 V), and the AD7671 and front-end preprocessing circuit (5 V), AMS1117 voltage regulator chips are designed for stable 5 V–1.2 V and 5 V–3.3 V power supplies. In the experiments, wavelength calibration and spectral preprocessing are performed on the system prior to data processing. Near-infrared reflectance spectra of different skin conditions (melanoma, vitiligo) are compared with normal skin. The results demonstrate the accurate assessment capability of the designed infrared optoelectronic skin detection system. Facial skin data obtained from the system are used to generate facial images, and the recognition performance of different detection systems is compared in an algorithmic environment, thereby demonstrating the promising application prospects of the infrared optoelectronic skin detection system in the field of facial recognition.

Analysis and Suppression of Rectifier Diode Voltage Oscillation Mechanism in IPOS High-Power PSFB Converters

Parasitic oscillations in the rectifier diode voltage of phase-shifted-full-bridge (PSFB) converters limit their application in high-voltage and high-power situations. The conventional analysis method for parasitic oscillation in rectifier diode voltage in PSFB converters treats the filter inductor as a constant current source and fails to consider the impact of changes in filter inductor current on the rectifier diode’s parasitic oscillation. Consequently, this approach does not apply when analyzing the rectifier diode voltage’s parasitic oscillations in high-power PSFB converters employing an input-parallel output-series (IPOS) configuration with interleaved drive. This research paper introduces an innovative equivalent circuit model for analyzing the parasitic oscillations of rectifier diode voltage in IPOS high-power PSFB converters. The model takes into account the mutual influence of rectifier diode voltage oscillations between submodules under interleaved control, considering the influence of changes in filter inductor current on rectifier diode parasitic oscillation. Based on the circuit model, we explain the mechanism of multiple oscillations of the rectifier diode voltage and the reason for the high peak of the first oscillation. Consequently, the interplay of rectifier diode voltage oscillations in IPOS high-power k-module PSFB converters under interleaved control is analyzed. To mitigate the adverse effects of rectifier diode voltage parasitic oscillation, a buffering strategy involving the connection of a resistor capacitor diode (RCD) circuit in parallel after the rectifier bridge is adopted, considering the structure of the IPOS high-power PSFB converter. The study provides a detailed analysis of the circuit’s operation mechanism upon incorporating the RCD buffer circuit and establishes the relationship between buffer capacitance, resistance, and spike voltage. Furthermore, a design method for buffer capacitors and discharge resistors in buffer circuits is presented. Finally, a 100 kW prototype is tested to verify the rectifier diode voltage oscillation mechanism of the IPOS high-power PSFB converter and the rationality of the buffer capacitor and discharge resistor design method under the interleaved drive approach.

Simple-Structure Active Lossless Decoupling Rectifier With Automatic PFC

One of the main challenges is how to prolong the lifetime of converters, and as in most single-phase converters the need for electrolytic capacitors. A simple structure rectifier is proposed with lossless buffer and power factor correction (PFC) abilities. It has the advantages of low cost, fewer auxiliary components, and high conversion efficiency. The active buffer circuit as an auxiliary unit consists of just one capacitor and one switch. It not only makes it possible for the rectifier to operate without electrolytic capacitors but also provides zero voltage switching (ZVS) for the buffer tank. Additionally, a simple control scheme is presented, in which near perfect power factor is obtained. Finally, the operating principles, control methods, and design guidelines are presented in detail, and the feasibility of the proposed converter is verified through a 58-W (48-V/1.2-A) hardware prototype. All the superior performances of the proposed rectifier are verified by the experimental prototype.

High Performance Energy-Efficient Leakage-Tolerant Dual Keeper Pseudo Domino Logic

In this paper, an improved high performance energy-efficient leakage-tolerant dual keeper pseudo domino logic circuit is proposed. Circuit design methodologies such as pseudo domino, stacking effect and inverted clock-controlled dual keeper are used in the proposed work for significant reduction of the circuit’s propagation delay and leakage current. Using pseudo-domino logic voltage swing at the output is reduced, stacking effect reduces the leakage current and charge sharing issues in the circuit are reduced by an inverted clock-controlled dual keeper circuit. Leakage current in the proposed circuit is decreased by 21.9%, 20.8%, 71.6%, 52.4% and 57.5% to the conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic, respectively at a 27°C temperature and 1GHz clock frequency. Similarly, delay in the proposed circuit is reduced by 83.3%, 80.1%, 89.8%, 81.3% and 81.5% in comparison to conventional logic, DOIND logic, DVT DOIND logic, DFD logic and C3D domino logic circuit, respectively. Performance metrics like power dissipation, delay, PDP, leakage current, static power, and EDP of the proposed circuit are analysed and compared with the existing domino logics. Monte-Carlo simulation is performed using 1000 samples to analyse the performance of the proposed circuit. The proposed logic circuit is also tested against temperature and process variations. The median values of the proposed buffer circuit’s power and delay are 5.6µW and 1.28ps, respectively and the standard deviation of average power and propagation delay are 633.62nW and 84.37fs, respectively at 27°C and 1GHz clock frequency.

Low Leakage CMOS Design Technique with Stable State Retention

In this research, a new hybrid design technique for low-power complementary metal–oxide semiconductor (CMOS) circuits is proposed which utilizes the advantages of multiple design methodologies such as sleep-transistors, forced-stack, and variable-threshold CMOS (VTCMOS), and is integrated with a buffer circuit. Based on the proposed technique, the CMOS inverter and two-input NAND circuits are simulated in LTspice software using 16 nm high-performance (HP) and low-power (LP) predictive technology models (PTM). Upon comparison with available leakage reduction techniques, the proposed approach demonstrates considerably low power, delay and power delay product (PDP) while maintaining output-logic integrity. The impact of the process parameter, voltage, and temperature (PVT) variations are observed through Monte Carlo simulations, which depict that the proposed model provides uniform sensitivity in terms of the performance metrics within ±3σ statistical variations from the mean. The circuit area of the proposed technique is also estimated and compared with existing methods using the Cadence Virtuoso platform.

A 10-Bit 20 Channel LCD Column Driver Using Compact DAC

A 20-channel liquid crystal display (LCD) driver architecture is implemented with [Formula: see text]m CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using [Formula: see text]m CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140[Formula: see text]dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25–1.7[Formula: see text]V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and −0.12 LSB, respectively. The one channel area is [Formula: see text]m and the settling time is [Formula: see text]s for the [Formula: see text] and 20[Formula: see text]pF driving load.

Operation Characteristics of Discontinuous Current Mode for a Dual-Active-Bridge AC-DC Converter with an Active Energy Buffer

This paper discusses operation characteristics of discontinuous current mode (DCM) for an ac-dc isolated converter for on-board battery chargers of electric vehicles. The converter discussed in this paper consists of a front-end diode-bridge rectifier, an active energy buffer, and a dual-active-bridge dc-dc converter. The energy buffer circuit absorbs the power pulsation form the single-phase ac line into a small-rated capacitor, and thus, makes it possible to reduce a required capacitance of the dc-link capacitor. This paper explains details of the DCM control method including a technique of the ripple cancel of the inductor current, to realize the power factor correction of the line current and the voltage control of the buffer capacitor at the same time without complex calculations. Then, a reference value of the inductor current and an operation range of the dc-output voltage are discussed. Experimental results obtained by a 220-V, 6.6-kW experimental setup demonstrate a sinusoidal-line current and a controlled buffer capacitor voltage as well as a smoothed dc-output current.

A Second-Order Voltage Ripple Suppression Strategy of Five-Level Flying Capacitor Rectifiers Under Unbalanced AC Voltages

Unbalanced ac voltages drastically deteriorate the performance of five-level flying capacitor (FC) rectifiers. Without introducing an extra buffering circuit to absorb the second-order oscillating power, it is an incompatible contradiction for realizing both negative-sequence current reduction and second-order voltage ripple suppression. In this article, based on the idea of using FCs in the rectifier to absorb the oscillating power, a second-order voltage ripple suppression strategy for unbalanced ac voltage conditions is proposed. Reducing the negative-sequence currents and suppressing the dc voltage ripples can be simultaneously realized. Simulations and experimental results verified the effectiveness and performance of the proposed scheme well.

Fast protection strategy for monopole grounding fault of low-voltage DC microgrid

• This paper presents a low-voltage DC microgrid ground short-circuit fault protection system based on positive channel metal oxide semiconductor (PMOS). • In case of ground short-circuit fault in DC microgrid, the coupling energy of the short-circuit current makes the PMOS to be turned off reliably. • In addition, because the primary inductance of the transformer plays a certain current limiting role, the turn-off current of PMOS will not increase sharply. Low voltage DC microgrid has attracted more and more attention in smart grid with its advantages such as low network loss, large transmission capacity and easy direct access to distributed power supply. However, compared with the traditional AC microgrid, the DC microgrid lacks inertia support and the fault develops rapidly, which makes the existing short-circuit current protection technology difficult to meet the requirements of accurate and efficient troubleshooting. Therefore, this paper presents a low-voltage DC microgrid ground short-circuit fault protection system based on positive channel metal oxide semiconductor (PMOS) self-powering DC solid-state circuit breaker protection elements, and verifies the feasibility and effectiveness of the protection system through simulation experiments. The experimental results show that the proposed protection system based on solid state circuit breaker will not affect the voltage of DC microgrid when it is normally on; In case of ground short-circuit fault in DC microgrid, the coupling energy of the short-circuit current makes the PMOS to be turned off reliably. In addition, because the primary inductance of the transformer plays a certain current limiting role, the turn-off current of PMOS will not increase sharply. The solid-state circuit breaker can effectively block the fault without a buffer circuit, which has a good application prospect.

Prediction of Power Supply Induced Jitter With PDN Design Parameters

This article proposes a method to predict power supply induced jitter (PSIJ) at the inverter chain buffer output with the design parameters of power distribution network (PDN). The PDN is assumed to contain multiple decoupling capacitors with sufficiently different values for each branch. The relationship between PSIJ and PDN design parameters is derived analytically by convoluting the time-domain voltage ripple with the buffer time-domain PSIJ sensitivity, given the triangular noise current information. The analytical formula is validated through measurement by using an in-house designed CMOS buffer circuit and a controllable aggressor circuit based on 180 nm technology. The buffer output PSIJ under the operation of the aggressor circuit and the corresponding switching noise current are characterized. The <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R–L–C</i> design parameters of PDN are extracted through impedance measurement. With the PDN parameters, the output jitter is calculated with the derived formulation. Compared with the measurements, the prediction error of the proposed method is within 8.1% when the voltage ripple amplitude is no larger than 10% of the supply voltage.