Buffer Circuit Research Articles

CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices

The incompatibility between current RFID standards has led to the need for universal and Wi-Fi compatible RFID for IoT applications. Such a universal RFID requires an SPDT and an LNA to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from bulky die area, lesser Q factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, nano-CMOS inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83dB insertion loss, a 45.3dB isolation, and a 11.3dBm power-handling capacity whereas the LNA achieves a peak gain of 33dB, bandwidth of 30MHz and NF of 6.6dB at 2.45GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003mm 2 and 127.7 μm 2 , respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology.

Improved Target Impedance Concept With Jitter Specification

In this article, an improved target impedance concept directly correlating circuit output jitter with power distribution network (PDN) R-L-C parameters is proposed. A systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. The relationship between output jitter and PDN R-L-C parameters is analytically derived by evaluating the time domain voltage ripple to jitter transfer relationship along with the relationship between time domain voltage ripple and PDN R-L-C parameters. Given the transient integrated circuit switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The jitter and PDN R-L-C analytical correlations are validated through HSPICE simulation. The application of the proposed target impedance concept with jitter specification is also demonstrated via simulation.

A PM2.5 Sensor Module Based on a TPoS MEMS Oscillator and an Aerosol Impactor

In this work, a real-time PM2.5 sensor module with high mass resolution and wide detection range is successfully demonstrated while the module consists of a two-stage aerosol impactor, a Thin-film Piezoelectric-on-Silicon (TPoS) MEMS oscillator, and a micro-pump. The aerosol impactor's collection efficiency of 51% for $2.54~\mu \text{m}$ and 50% for $1.03~\mu \text{m}$ is verified for stage 1 and stage 2, respectively. A length-extensional mode TPoS MEMS resonator is implemented, featuring a resonant frequency of 4.05 MHz and a quality factor (${Q}$ ) of 438 in air. To achieve a portable sensor module, a board-level sustaining circuit, which includes a transimpedance amplifier (TIA), a phase shifter, a band-pass filter, and a buffer circuit are integrated to fulfill the condition of Barkhausen criteria for oscillation. Phase noise of -111.92 dBc/Hz at 1 kHz offset was recorded under ambient pressure and room temperature for a carrier frequency of 4.05 MHz. The mass resolution for the PM2.5 sensor implemented in this work is 0.71 pg. Finally, an incense was used to produce the liquid type particles continuously for the aerosol measurement. The coefficient of determination (${R} ^{2}$ ) of 0.81 between the frequency slope of the proposed sensor and the aerosol concentration of the commercial optical aerosol sensor within a range of $10~\mu $ g/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> to $1000~\mu $ g/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> . This work successfully integrated MEMS, circuit, and air flow technologies to realize a complete mass sensing module, and has the potential to be implemented in the particulate matter concentration monitoring applications of air.

Busbar Design and Optimization for Voltage Overshoot Mitigation of a Silicon Carbide High-Power Three-Phase T-Type Inverter

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

Optimized buffer insertion for efficient interconnects designs

AbstractThis typescript focuses on unraveling the functional performance deterioration issues related to conventional Cu on‐chip nanointerconnecting wires; mainly occurred due to the shrinking of device dimensions. Buffer insertion methodology proves to be an effective approach for designing high‐speed interconnect network but at the cost of power consumption. Moreover, ramification of too many buffers as repeaters leads to area overhead. Hence an optimized number must be judicially decided. Proposed circuits for buffers are modeled using variable diameter and multi Vt design techniques to balance delay as well as average power consumption. Interconnects designed with conventional Cu interconnect technology are compared with state of art CNT technology at different lengths. Proposed and Existing Buffer circuit architectures are modeled with both CNT and MOS technology to carry out the comparative simulation analysis using varied combination of CNTFET buffer‐CNT interconnect and CMOSFET buffer‐Cu interconnect. Benchmarking with conventional buffer circuits, simulated results illustrates that ProposedBuffer1 saves dynamic power by 89.96%, leakage power by 89%, and offers delay mitigation by 77.5%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 97.53%, but causes delay penalty. All the HSPICE simulations are carried out using Stanford SPICE model for CNT and BSIM4 PTM for MOS at 32 nm.

Design and implementation of low power dynamic buffer circuit for nanotechnology application

The currently used standard domino logic circuits in most of the nanotechnology application consume more power due to redundant switching (charging and discharging of capacitance). Further, at the output node, logic‘1’ is only for half the input cycle rather than the full cycle. To overcome these disadvantages, two conventional circuits were designed namely, True Single Phase Clock (TSPC) and Limited Switch Dynamic Logic (LSDL) to reduce the redundant switching of the standard domino logic. But these two conventional circuits had their own drawbacks. The LSDL circuit consists of more number of transistors which in turn consumes more power and chip area. The TSPC also has an increased power consumption and load capacitance due to three clock transistors in the circuit. To overcome the disadvantage of the conventional circuits, in this work we propose anew circuit which minimizes redundant switching at the output node as well as it utilizes the leakage voltages within the circuit to drive the output stage. As a result, our proposed circuit consumes only 0.8821 µW power compared to standard domino logic circuit which consumes 1.973 µW which means a 55.29% power reduction compared to standard domino logic. The proposed circuit is implemented in AND Gate, OR Gate and Full Adder, resulting in a significant power reduction compared to standard domino logic implemented in AND Gate, OR Gate and Full Adder circuit.

Impaired Tubular Reabsorption Is the Main Mechanism Explaining Increases in Urinary NGAL Excretion Following Acute Kidney Injury in Rats.

Neutrophil gelatinase-associated lipocalin (NGAL) is a secreted low-molecular weight iron-siderophore-binding protein. NGAL overexpression in injured tubular epithelia partly explains its utility as a sensitive and early urinary biomarker of acute kidney injury (AKI). Herein, we extend mechanistic insights into the source and kinetics of urinary NGAL excretion in experimental AKI. Three models of experimental AKI were undertaken in adult male Wistar rats; renal ischemia-reperfusion injury (IRI) and gentamicin (G) and cisplatin (Cisp) nephrotoxicity. Alongside standard histological and biochemical assessment of AKI, urinary NGAL excretion rate, plasma NGAL concentration, and renal NGAL mRNA/protein expression were assessed. In situ renal perfusion studies were undertaken to discriminate direct shedding of NGAL to the urine from addition of NGAL to the urine secondary to alterations in the tubular handling of glomerular filtrate-derived protein. Renal NGAL expression and urinary excretion increased in experimental AKI. In acute studies in both the IRI and G models, direct renal perfusion with Kreb's buffer eliminated urinary NGAL excretion. Addition of exogenous NGAL to the Kreb's buffer circuit, reestablishment of perfusion with systemic blood or reperfusion with renal vein effluent restored high levels of urinary NGAL excretion. Urinary NGAL excretion in AKI arises in large proportion from reduced reabsorption from the glomerular filtrate. Hence, subclinical cellular dysfunction could increase urinary NGAL, particularly in concert with elevations in circulating prerenal NGAL and/or pharmacological inhibition of tubular reabsorption. More granular interpretation of urinary NGAL measurements could optimize the scope of its clinical utility as a biomarker of AKI.

Electronically tunable DV-EXCCCII-based universal filter

ABSTRACT A new analog block, Differential Voltage Extra-X Current Controlled Conveyor (DV-EXCCCII) based current mode universal filter configuration is introduced in this paper. Only one current mode analog block DV-EXCCCII, three grounded components are used to design proposed filter configuration. This circuit provides high output impedance, which allows cascading feature to circuit without need of extra buffer circuit. This configuration realise all five (Low Pass, High Pass, All Pass, Band Pass and Band Reject) second-order filter functions with an appropriate selection of input. Bias current of DV-EXCCCII provides the electronic tuning characteristic to proposed circuit. Sensitivity due to passive components and non-idealities of the analog block is low and magnitude is below unity. The proposed filter circuit configuration is designed in CADENCE and simulated with SPECTRE using 180 nm UMC CMOS process technology.

Toward Impedimetric Measurement of Acidosis with a pH-Responsive Hydrogel Sensor.

A pH-responsive, poly(2-hydroxyethyl methacrylate) [poly(HEMA)]-based hydrogel has been fashioned into an impedimetric pH sensor for the continual measurement and monitoring of tissue acidosis that can arise due to hemorrhaging trauma. Four hydrogel systems molecularly engineered to influence water distribution and ionic abundance were studied: a cationogenic primary amine, N-(2-aminoethyl) methacrylate (AEMA), a tertiary amine moiety, N,N-(2-dimethylamino)ethyl methacrylate (DMAEMA), and a combined AEMA-DMAEMA formulation. Electrochemical impedance spectroscopy (EIS) of hydrogel discs held between platinized Type 304 stainless steel mesh electrodes in pH-adjusted 4-(2-hydroxyethyl)-1-piperazineethanesulfonic acid sodium salt (HEPES) buffer and equivalent circuit modeling indicated that the AEMA hydrogel had the highest sensitivity containing the relevant pathophysiological range (pH 7.0-8.0). Thus, the AEMA formulation was studied at 0, 1, 3, 4.4, and 30 mol % AEMA. The 1 mol % AEMA was found to significantly (p < 0.05) discern nominal pH (7.35, 7.40, 7.45). The Taguchi Design of Experiments approach was employed and confirmed composition as a factor and 1 mol % AEMA to be the most robust. DMAEMA (0, 4.4, 14, 30 mol %) and AEMA-DMAEMA (0, 4.4, 14, 30 mol %) allowed the use of the one-factor Response Surface Methodology optimizer to confirm the AEMA 1 mol % system to be most robust, sensitive, and possessing optimal sensitivity in the pathophysiological pH sensing range (7.35-7.45) for hemorrhagic trauma. This composition was fashioned as a responsive membrane on a microlithographically fabricated interdigitated microsensor electrode and the sensitivity was determined using R(QR)(QR) analysis. Water distribution within the AEMA (0, 1, 4.4, 30 mol %), determined by gravimetric analysis and differential scanning calorimetry, revealed a strong anticorrelation between nonfreezable bound water and pH sensitivity (-0.82) and was in good agreement with the total hydration (-0.70). Nonfreezable bound water was found to be the most strongly correlated factor that governs the pH response of hydrogels.

Designing dual-chirality and multi-Vtrepeaters for performance optimization of 32 nm interconnects

PurposeThis paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vttechnology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm.Design/methodology/approachUsually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vttransistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control.FindingsAn unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes.Originality/valueResult analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

Simulation and experiment of a new DC fault current limiter topology

With the development of high voltage direct current (HVDC) power transmission system, it is imperative to develop a practical current limiting device which can effectively protect the converter from the influence of fault current. Based on the topology of current limiter proposed in previous papers, considering the requirements of practical application conditions, an optimized topology is proposed, which consists of snubber circuit and arrester, both in simulation and experiment. In addition, the RC buffering circuit is added and the parameters are optimized to reduce the voltage impulse that the IGBT of fault current limiter would else bear. Simulation and experiment are carried out in DC system. Both simulation and experiment results can prove the effectiveness of the optimized current limiter circuit.

Interfacing TTL and CMOS Logic Levels in the Laboratory

ABSTRACT Interconnectivity of electrical components, such as triggers and detectors, is intrinsic to operating time-sensitive experiments. As labs become more digitized, equipment integration and compatibility become larger factors in experimental setups. Complications can arise when instruments with different signal levels, or logic levels, are integrated because each instrument requires its own particular input signal, with a specific threshold voltage, to function. When incorrect logic levels are used or the delays in conversion are too long, these instruments are not properly triggered and the experiment becomes inoperable. To perform multi-component, time-sensitive experiments, a logic-level converter with minimal time delays is necessary. Commercial solutions, however, are not viable when the nature of the experiment is highly time-sensitive, such as in laser spectroscopy, because the delay on the signal conversion is several hundred nanoseconds and would result in missed events. In this paper, three different logic-level converter circuits are presented for conversion between the TTL and CMOS logic levels, the most commonly used logic levels in experimental applications, based on the concept of an emitter follower design that only produces a delay in the tens of nanoseconds. Circuits were developed for conversion from CMOS to TTL, from TTL to CMOS, and a TTL buffer circuit. These circuits allow for inter-conversion between the two most common logic families, TTL and CMOS, as well as buffering weak signals, to offer a simple, low-cost solution to synchronization in time-sensitive experimental setups.

Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to super-threshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to superthreshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

Design and Development of Driver Protection Circuit of Self Turn off Devices Applies to Electric Vehicle Fast-Change Mode

In this paper, based on the design of the chip UAA4002 one for electric vehicle fast charge mode of self-turn-off device driver protection circuitry to power transistor, for example, study design optocoupler isolation circuit, control circuit, anti-saturation circuit, composite buffer circuit, Further integration of the formation of self-turn-off device drivers, isolation, protection circuit, which has a simple circuit structure, function, high reliability, low switching losses, fast response.

Two-Wired Active Spring-Loaded Dry Electrodes for EEG Measurements.

Dry contact electrode-based EEG acquisition is one of the easiest ways to obtain neural information from the human brain, providing many advantages such as rapid installation, and enhanced wearability. However, high contact impedance due to insufficient electrical coupling at the electrode-scalp interface still remains a critical issue. In this paper, a two-wired active dry electrode system is proposed by combining finger-shaped spring-loaded probes and active buffer circuits. The shrinkable probes and bootstrap topology-based buffer circuitry provide reliable electrical coupling with an uneven and hairy scalp and effective input impedance conversion along with low input capacitance. Through analysis of the equivalent circuit model, the proposed electrode was carefully designed by employing off-the-shelf discrete components and a low-noise zero-drift amplifier. Several electrical evaluations such as noise spectral density measurements and input capacitance estimation were performed together with simple experiments for alpha rhythm detection. The experimental results showed that the proposed electrode is capable of clear detection for the alpha rhythm activation, with excellent electrical characteristics such as low-noise of 1.131 μVRMS and 32.3% reduction of input capacitance.

A Binary Line Buffer Circuit Featuring Lossy Data Compression at Fixed Maximum Data Rate

Video processing requires an increasing amount of buffered data. The paper proposes a multi-line buffer circuit that stores compressed data thus saving logic and power. The lossy compression algorithm provides the output stream with a fixed, decided by the user, delay from the input stream. Further, the amount of memory of the compressed buffer can be designed to trade off the correctness of the output with the logic resources footprint. The circuit is tested in a computer vision processing chain as a binary line buffer for the stream of foreground pixels. The paper also proposes a multi-line buffer circuit that integrates a morphological operation. The latter, when compared against the state of the art and against the proposed multi-line lossy buffer, allows larger saving of logic resources (up to 75%) and power (up to 85%), with reduced penalty on video quality.

Simulation of a Low Cost Single Phase to Three Phase Converter using Arduino

This paper proposes a single phase to three phase conversion system composed of a rectifier, capacitive filter, Arduino controller, resistive switching network, buffer circuit and amplifier circuit. The proposed topology permits to operate at different frequencies by changing the coding of Arduino pulse generator. Although the effectiveness of previous work is acknowledged, none have assessed the multilevel wave generation using arduino and resistive switching network. It reduces the cost by using resistive switching technique and better accuracy as the input pulse is divided into 20 steps and finally a stepped sine wave is obtained. This converter can be easily used for motors up-to 5HP. Analysis and simulated results are presented to validate these features.

ANALYSIS AND DESIGN OF A NEW STRUCTURE FOR 10-BIT 350MS/S PIPELINE ANALOG TO DIGITAL CONVERTER

A 10-bit pipelined Analog to Digital converter is proposed in this paper with using 0.18 µm TSMC technology. In this paper, a new structure is proposed to increase the speed of the pipeline analog to digital convertor. So at the first stage is not used the amplifier and instead the buffer is used for data transfer to the second stage. The speed of this converter is 350MS/s. An amplifier circuit with accurate gain of 6 and a very accurate unit gain buffer circuit that are open loop with a new structure were. used. In this Converter, the first 3 bits are extracted simultaneously with sampling. The proposed analog-to-digital converter was designed with the total power consumption 75mW using power supply of 1.8v.

Demonstrating the Scope of a Switched Supercapacitor Circuit for Energy Harvesting Powered Wireless Sensor Loads

This paper describes the design of a high-efficiency energy management system for low-power, low-voltage energy harvesting powered wireless sensor systems. With typical voltages of less than 1 V and power levels lower than 1 mW, there are significant challenges when applying energy harvesting sources to supply pulsed power levels of up to 120 mW at voltage levels of 1.8–4 V as required by wireless sensor loads. The proposed approach integrates energy storage elements within a voltage step-up circuit to produce a new high-efficiency energy management circuit that converts the energy produced by a low-power, low-voltage source into a series of high power pulses. An optimized switched supercapacitor energy buffer circuit including a self-powered control circuit is proposed. Efficiencies of up to 91% are shown for an indoor solar cell source with a power level of 0.5 mW, supplying an equivalent wireless sensor with pulsed power levels of 10–120 mW. This is significantly higher than 83% achieved for the dc–dc stage of the existing best solution under the same source conditions, but requires an additional conversion step to provide high power pulses.