Design and implementation of low power dynamic buffer circuit for nanotechnology application

Abstract

The currently used standard domino logic circuits in most of the nanotechnology application consume more power due to redundant switching (charging and discharging of capacitance). Further, at the output node, logic‘1’ is only for half the input cycle rather than the full cycle. To overcome these disadvantages, two conventional circuits were designed namely, True Single Phase Clock (TSPC) and Limited Switch Dynamic Logic (LSDL) to reduce the redundant switching of the standard domino logic. But these two conventional circuits had their own drawbacks. The LSDL circuit consists of more number of transistors which in turn consumes more power and chip area. The TSPC also has an increased power consumption and load capacitance due to three clock transistors in the circuit. To overcome the disadvantage of the conventional circuits, in this work we propose anew circuit which minimizes redundant switching at the output node as well as it utilizes the leakage voltages within the circuit to drive the output stage. As a result, our proposed circuit consumes only 0.8821 µW power compared to standard domino logic circuit which consumes 1.973 µW which means a 55.29% power reduction compared to standard domino logic. The proposed circuit is implemented in AND Gate, OR Gate and Full Adder, resulting in a significant power reduction compared to standard domino logic implemented in AND Gate, OR Gate and Full Adder circuit.