Brent-Kung Adder Research Articles

A comprehensive review on the VLSI design performance of different Parallel Prefix Adders

Adders are an important part of digital systems. In VLSI digital circuits, such adders should satisfy certain design constraints like low power and high speed. In this paper we present a review of the performance of some conventional adders and parallel adders. Parallel Prefix Adders (PPA) are considered to be one of the fastest adders that had been designed and developed. Parallel Prefix Adders were established as the most efficient circuits for binary addition. These adders which are also called Carry Tree Adders were found to have better performance in VLSI designs. This paper investigates the performance of four different Parallel Prefix Adders namely Kogge Stone Adder (KSA), Brent Kung Adder (BKA), Han Carlson Adder (HCA) and Hybrid Han Carlson Adder (HHCA). In this paper the key contribution is the information about the structure of the Parallel Prefix Adders and their performance parameters. This paper can serve as a reference to the beginners in the digital electronics and VLSI area to gain more knowledge on the Carry Tree Adders.

Design and Implementation of High Speed Area Efficient Carry Select Adder Using Spanning Tree Adder Technique

In this paper, we propose Carry Select Adder (CSLA) architecture with parallel prefix adder. Instead of using 4-bit Brent Kung Adder (BKA), another parallel prefix adder i.e., 4-bit spanning Tree (ST) adder is used to design CSA. Because Adders are key element in digital design, which are not only performing addition operation, but also many other function such as subtraction, multiplication and division. A Ripple Carry Adder (RCA) gives the most complicated design as-well-as longer computation time so that we may gone for parallel prefix adders. This time critical application we use Spanning tree parallel prefix adder to drive fast results but they lead to increase in area. Proposed Carry Select Adder understands between RCA and BKA in term of area and delay. Delay of Existing adders is larger therefore we have replaced those with Brent Spanning Tree parallel prefix adder which gives fast result. This paper describes comparative performance of 4-bit RCA and 4-Bit BK parallel prefix adders with Our Proposed Spanning Tree adder based carry select adder designed using Xilinx ISE tool.

LOW POWER CIRCUIT FOR BRENT-KUNG ADDER BASED ON ADIABATIC LOGIC

Adiabatic logic circuit designs are used to reduce power dissipation in any circuits. For low power and low noise emission applications, adder plays a vital role. The Complementary Metal Oxide Semiconductor (CMOS) design of 16-bit Brent-kung adder provides less number of gates but it generates high power due to switching activities of the design. To overcome this problem, 16-bit Brent-kung adder is designed using complementary Pass Transistor Energy Recovery adiabatic Logic (CPERL) with less number of gates. Also, low power dissipation is achieved which can be used for long life battery operations. The CPERL based system offers 59.97% reduction in power when compared to the conventional design. Experimental results are obtained using TANNER EDA tool 13.1.

Comparative Analysis of High Speed Carry Skip Adders

In this paper we compared a high speed carry skip adders by considering parameters such as area, LUT’S, delay, power. When compared to conventional CSKA and other adders. Here in this project in first stage CSKA designed by using multiplexer as skip logic so by using this speed gets increased by skipping of carry. so here area gets increased so to reduce area another hybrid variable latency carry skip adder(Brent-kung adder) is designed .here power utilization also gets decreased, speed gets increased, but some delay is produced here to overcome that we followed a another method called Kogge-Stone adder here so it reduces the critical path delay. In Kogge-stone adder power is highly consumed due to more no of wiring connections so another adder was designed to reduce power consumption which is Sklansky adder which reduces power Consumption. This is done in Xilinx ISE 14.7 and power was analyzed using Xilinx power analyzer.

Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic

Superconductor-based adiabatic quantum-flux-parametron (AQFP) logic holds tremendous promise toward building extremely energy efficient computing systems with bit energies approaching 100 $k_B \text{T}$ . The majority logic gate is the basis for how all AQFP logic gates are created. By reconsidering the logic design approach of digital circuits using majority logic instead of conventional AND/OR/NOT logic, circuits can potentially use fewer gates overall. This may lead to lower circuit complexities in terms of Josephson junctions, and in turn lower power consumption as well as lower latencies. As a first step toward exploiting majority logic in AQFP technology, we explore how majority-logic-optimized designs of the Kogge–Stone and Brent–Kung adder architectures scale in terms of complexity, latency, area, and energy/operation as we increase the data word size from 8 to 64 bit. Next, we implement 8-bit prototypes of both adders for experimental demonstration. The designs have been fabricated using the 2.5 kA/ $\text{cm}^{2}$ AIST standard process 2 and have demonstrated successful operation in low-frequency testing. Both adders consist of $\sim$ 1000 Josephson junctions and are designed for 5 GHz operation with a five-cycle latency.

Implementation of 32-Bit Carry Select Adder using Brent-Kung Adder

The circuit used to add the two numbers or two bits is adder. The main problem with the adder is both the area and delay to produce the final output. So, this paper implements an adder it requires a less amount of delay and area to produce the final output. The reduction of delay and area is done by the Parallel Prefix Adders. It plays a prominent role in Digital Combinational Circuits. Area and power are other factors which really makes the adder effective. The techniques used to get a less amount of delay and area is by using the Binary-to-Excess-1 Converter (BEC) and a Parallel Prefix Adder. The delay of the Modified Linear Carry Select Adder of Brent Kung Adder is less when compared with the Regular Carry Select Adder architecture. The delay and area further can be improved by using a Square root Carry Select adder. This paper focuses on operation of Parallel Prefix Adders of 32 bit Brent-Kung Adder. Keywords: And-Or-Inverter (AOI) Logic, Binary-to-Excess-1 Converter (BEC), Brent-Kung (BK) Adders, Carry Select Adder (CSLA), Parallel Prefix Adder

Design Of A Optimized Parallel Array Multiplier Using Parallel Prefix Adder

Abstr act Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexit ies of algorith ms used in Digital Signal Processors (DSPs) have gradually increased. This requires a parallel array mu ltiplier to achieve high execution speed or to meet the performance demands. A typical imp lementation of such an array mu ltiplier is Braun design. Braun mult iplier is a type of parallel array mult iplier. The architecture of Braun mu ltip lier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. In this research wo rk, a new design of Braun Multiplier is proposed and this proposed design of mult iplier uses a very fast parallel p refix adder (Brent kung Adder) in place of Ripple Carry Adder. The architecture of standard Braun Multiplier is modified in this work for reducing the area and delay due to Ripple Carry Adder and performing faster mu ltiplication of two binary numbers. The design is imp lemented using Microwind1, dig ital schemat ics (DSCH)

Design of Adders using QCA

Quantum-dot cellular automata (QCA) is considered as an advanced technology compared to complimentary metal-oxide-semiconductor (CMOS) due to QCA’s merits.Many logical circuits are designed using QCA which consume low power.Therfore our interest is on desiging of adders using QCA. In this paper we present a number of new results on adders.Thus we design adders and detailed simulation using QCAD designer is presented.The performance of proposed adder gives the better Delay performance compared to Ripple carry adder(RCA).Thus we show that Brent-kung Adder has lower Delathen most of the proposed advanced adders.

Design and implementation of Parallel Prefix Adders using FPGAs

Adders are known to have the frequently used in VLSI designs. In digital design we have half adder and full adder, main adders by using these adders we can implement ripple carry adders. RCA use to perform any number of addition. In this RCA is serial adder and it has commutation delay problem. If increase the ha&fa simultaneously delay also increase. That's why we go for parallel adders(parallel prefix adders). IN the parallel prefix adder are ks adder(kogge-stone),sks adder(sparse kogge-stone),spaning tree and brentkung adder. These adders are designd and implemented on FPGA sparton3E kit. Simulated and synthesis by model sim6.4b, Xilinx ise10.1.

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

We propose a low-overhead fault-secure parallel prefix adder. We duplicate carry bits for checking purposes. Only one half of normal carry bits are compared with the corresponding redundant carry bits, and the hardware overhead of the adder is low. For concurrent error detection, we also predict the parity of the result. The adder uses parity-based error detection and it has high compatibility with systems that have parity-based error detection. We can implement various fault-secure parallel prefix adders such as Sklansky adder, Brent-Kung adder. Han-Carlson adder, and Kogge-Stone adder. The area overhead of the proposed adder is about 15% lower than that of a previously proposed adder that compares all the carry bits.

Design of 32 bit Parallel Prefix Adders

In this paper, we propose 32 bit Kogge-Stone, Brent-Kung, Ladner-Fischer parallel prefix adders. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages compare to other adders. Parallel prefix adders are faster and area efficient. Parallel prefix adder is a technique for increasing the speed in DSP processor while performing addition. We simulate and synthesis different types of 32-bit prefix adders using Xilinx ISE 10.1i tool. By using these synthesis results, we noted the performance parameters like number of LUTs and delay. We compare these three adders in terms of LUTs (represents area) and delay values. Keywords− prefix adder, carry operator, Kogge-Stone, Brent-Kung, Ladner-Fischer. I. Introduction Arithmetic circuits are the ones which perform arithmetic operations like addition, subtraction, multiplication, division, parity calculation. Most of the time, designing these circuits is the same as designing muxers, encoders and decoders. In electronics, an adder or summer is a digital circuits(7) that performs addition of numbers. In many computers and other kind of processors, adders are other parts of the processor, many computers and other kinds of processors, where they are used to calculate addresses, table and similar. The binary adder(7,10) is the one type of element in most digital circuit designs including digital signal processors(DSP) and microprocessor data path units. Therefore fast and accurate operation of digital system depends on the performance of adders (6). Hence improving the performance of adder is the main area of research in VLSI(10) system design. The Conventional adders discussed in section II. The details of R Kogge- Stone adder, Brent-Kung adder and Ladner- Fischer adders are discussed, and the implementation of proposed system is described in section III. The performance and simulation results were presented and discussed in section IV.

Design of High-Speed Adders for Efficient Digital Design Blocks

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for -bit RCA and -bit Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. We further show that the Brent-Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent-Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented.

Implementation and Performance Evaluation of Prefix Adders uing FPGAs

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. The binary adder is the critical element in most digital circuit designs including digital signal processors and microprocessor data path units. The final carry is generated ahead to the generation of the sum which leads extensive research focused on reduction in circuit complexity and power consumption of the adder. In VLSI implementation, parallel-prefix adders are known to have the best performance. This paper investigates four types of carry-tree adders (the Kogge-Stone, sparse Kogge-Stone, spanning tree, Brent kung Adder) and compare them to the simple Ripple Carry Adder and Carry Skip Adder. These designs of varied bit-widths are simulated using model-sim simulator of 6.4 version and implemented on a Xilinx 10.1 version Spartan 3E FPGA. These fast carry-chain carry-tree adders support the bit width up to 256. We report on the area requirements and reduction in circuit complexity for a variety of classical parallel prefix adder structures. Keywords-FPGA, Prefix Adder, ALU, Xilinx, VLSI, CLA, Simulation, Synthesis

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic

Two-operand binary addition is the most widely used arithmetic operation in modern datapath designs. To improve the efficiency of this operation, it is desirable to use an adder with good performance and area tradeoff characteristics. This paper presents an efficient carry-lookahead adder architecture based on the parallel-prefix computation graph. In our proposed method, we define the notion of triple-carry-operator, which computes the generate and propagate signals for a merged block which combines three adjacent blocks. We use this in conjunction with the classic approach of the carry-operator to compute the generate and propagate signals for a merged block combining two adjacent blocks. The timing-driven nature of the proposed design reduces the depth of the adder. In addition, we use a ripple-carry type of structure in the nontiming critical portion of the parallel-prefix computation network. These techniques help produce a good timing-area tradeoff characteristic. The experimental results indicate that our proposed adder is significantly faster than the popular Brent-Kung adder with some area overhead. On the adder hand, the proposed adder also shows marginally faster performance than the fast Kogge-Stone adder with significant area savings.