Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic

Abstract

Superconductor-based adiabatic quantum-flux-parametron (AQFP) logic holds tremendous promise toward building extremely energy efficient computing systems with bit energies approaching 100 $k_B \text{T}$ . The majority logic gate is the basis for how all AQFP logic gates are created. By reconsidering the logic design approach of digital circuits using majority logic instead of conventional AND/OR/NOT logic, circuits can potentially use fewer gates overall. This may lead to lower circuit complexities in terms of Josephson junctions, and in turn lower power consumption as well as lower latencies. As a first step toward exploiting majority logic in AQFP technology, we explore how majority-logic-optimized designs of the Kogge–Stone and Brent–Kung adder architectures scale in terms of complexity, latency, area, and energy/operation as we increase the data word size from 8 to 64 bit. Next, we implement 8-bit prototypes of both adders for experimental demonstration. The designs have been fabricated using the 2.5 kA/ $\text{cm}^{2}$ AIST standard process 2 and have demonstrated successful operation in low-frequency testing. Both adders consist of $\sim$ 1000 Josephson junctions and are designed for 5 GHz operation with a five-cycle latency.