Abstract
Abstr act Multiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexit ies of algorith ms used in Digital Signal Processors (DSPs) have gradually increased. This requires a parallel array mu ltiplier to achieve high execution speed or to meet the performance demands. A typical imp lementation of such an array mu ltiplier is Braun design. Braun mult iplier is a type of parallel array mult iplier. The architecture of Braun mu ltip lier mainly consists of some Carry Save Adders, array of AND gates and one Ripple Carry Adder. In this research wo rk, a new design of Braun Multiplier is proposed and this proposed design of mult iplier uses a very fast parallel p refix adder (Brent kung Adder) in place of Ripple Carry Adder. The architecture of standard Braun Multiplier is modified in this work for reducing the area and delay due to Ripple Carry Adder and performing faster mu ltiplication of two binary numbers. The design is imp lemented using Microwind1, dig ital schemat ics (DSCH)
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