Breakdown Spots Research Articles

Influence of Oxide Breakdown Percolation Resistance on MOSFETs (Invited Paper)

A method is developed to measure the effective resistance associated with a percolation path formed during gate oxide breakdown (BD). The evolution of percolation resistance (Rperc) and channel resistance (Rch) during progressive BD (PBD) is studied in details. Our results reveal that PBD is constituted by the Rperc- and the Rch-controlled region. Additionally, Rperc is found to be a temperature- and voltage-dependent parameter, implying that PBD under different stressing conditions could be governed by different mechanisms. According to finite element analysis and infrared photoemission microscopy, a high localized temperature in the vicinity of the BD spot could exist to trigger dopant redistribution and microstructural damages. The change in diode I-V characteristics at the substrate-source/drain junction acts as a signature for the occurrence of dopant redistribution. This is confirmed by the simulation results of TSUPREM. The narrow device structures further enhance the localized heating effect during BD due to heat confinement.

Structure and Conductance of the Breakdown Spot During the Early Stages of Progressive Breakdown

It has been shown that under accelerated stress below ap4 V, thin gate oxides are subject to progressive breakdown (BD), i.e., a gradual growth of the BD spot up to a destructive BD. This paper investigates the conduction mechanisms of the BD spot during the early stages of progressive BD through the measurement of the I-V characteristics using carrier separation. It is shown that a model with no free parameter based on the concept of cotunneling provides a good evaluation of the post-BD current. This model implies a physical microstructure, and its plausibility is compared to direct transmission electron microscopy (TEM) observations

Breakdown kinetics at nanometer scale of innovative MOS devices by conductive atomic force microscopy

The breakdown (BD) kinetics of dielectrics represent a crucial issue for the reliability of microelectronics devices. In this paper, we report on an innovative and practical approach based on Conductive Atomic Force Microscopy (C-AFM) for the determination of the BD kinetics on a bare insulator surface. This technique has been applied to Pr 2O 3 films grown by Metal-Organic Chemical Vapour Deposition (MOCVD) on Si(0 0 1) and to thermally grown SiO 2 on 4H–SiC substrates. C-AFM clearly visualizes single breakdown spots under constant voltage stresses. The stress time on the C-AFM tip was varied from 1 × 10 −3 to 1 × 10 −1 s. The density of BD spots, upon increasing the stress time, exhibits in both cases an exponential trend. The Weibull slope of the dielectric BD statistics has been determined by direct measurements at nanometer scale on different dielectrics having different physical thicknesses. The comparison of the Weibull slopes obtained for different dielectric thicknesses with literature data points out intrinsic and extrinsic BD events in the SiO 2/SiC system and Pr 2O 3 based layers, respectively. In the case of the SiO 2/SiC system, BD kinetics have been demonstrated to follow the percolation model, while the role of extrinsic phenomena in the BD of Pr 2O 3 films has been proved.

Study of Dopant Redistribution at the Substrate-Source/Drain p-n Junction of Nanoscale MOSFET During Progressive Breakdown

During the evolution of dielectric breakdown (BD) in MOSFETs, the substantial localized temperatures (which could exceed the silicon melting point) in the vicinity of the BD spot may cause dopants at the source/drain (S/D) to be redistributed (IEDM Tech. Dig., p. 717, 2004; IEEE Proc. IPFA, p. 131, 2005). The preliminary study of dopant redistribution based on the diode current-voltage (I-V) characteristics at the substrate-S/D p-n junction of a BD MOSFET was presented by Lim (IEEE Proc. IPFA, p. 131, 2005). The post-BD MOSFET diode current measured in the reverse bias as well as the low-voltage region of the forward bias was found to increase significantly as progressive BD evolves. The simulation results associated with the dopant redistribution are in good agreement with the experimental measurements. This confirms that the dopant redistribution is one of the dominant mechanisms responsible for the change in the post-BD MOSFET diode I-V characteristics. In addition, the dopant redistribution in a large-area long-channel BD MOSFET is found to be a function of BD location. However, the BD location dependence of the dopant redistribution will vanish in a narrow short-channel BD MOSFET

Reliability of thermally oxidized SiO2∕4H-SiC by conductive atomic force microscopy

The dielectric breakdown (BD) kinetics of silicon dioxide (SiO2) thin films thermally grown on 4H-SiC was determined by comparison between I-V measurements on large area (up to 1.96×10−5cm2) metal-oxide-semiconductor structures and conductive atomic force microscopy (C-AFM). C-AFM clearly images the weak breakdown single spots under constant voltage stresses. The stress time on the single C-AFM tip dot was varied from 2.5×10−3to1×10−1s. The density of BD spots, upon increasing the stress time, exhibits an exponential trend. The Weibull slope and the characteristic time of the dielectric BD events have been determined by direct measurements at nanometer scale allowing to demonstrate that the percolative model is valid for thermal oxide on 4H-SiC.

The post-damage behavior of a MOS tunnel emitter transistor

The effect of oxide damage on the characteristics of an Al/SiO 2/n-Si MOS tunnel emitter transistor, is considered. The pre-breakdown oxide degradation is shown to reduce the current gain and to extend the S-shape segment of the collector characteristic of a device. This kind of damage may be formally modeled as an increase of the SiO 2 thickness deviation. After a soft breakdown, the transistor usually loses its bistability and has much lower gain in the range of large currents, while in the low-current mode the device behavior remains almost unchanged. Essential is the size of the zone affected by a breakdown spot, which is, to a great extent, regulated by the conductivity of an inversion layer.

Dielectric breakdown mechanisms in gate oxides

In this paper we review the subject of oxide breakdown (BD), focusing our attention on the case of the gate dielectrics of interest for current Si microelectronics, i.e., Si oxides or oxynitrides of thickness ranging from some tens of nanometers down to about 1nm. The first part of the paper is devoted to a concise description of the subject concerning the kinetics of oxide degradation under high-voltage stress and the statistics of the time to BD. It is shown that, according to the present understanding, the BD event is due to a buildup in the oxide bulk of defects produced by the stress at high voltage. Defect concentration increases up to a critical value corresponding to the onset of one percolation path joining the gate and substrate across the oxide. This triggers the BD, which is therefore believed to be an intrinsic effect, not due to preexisting, extrinsic defects or processing errors. We next focus our attention on experimental studies concerning the kinetics of the final event of BD, during which the gate leakage increases above acceptable levels. In conditions of intrinsic BD, the leakage increase is due to the growth of damage within the oxide in localized regions. Observations concerning this damage are reviewed and discussed. The measurement of the current, voltage, and power dissipated during the BD transient are also reported and discussed in comparison with the data of structural damage. We then describe the current understanding concerning the dependence of the BD current transient on the conditions of electric field and voltage. In particular, as the oxide thickness and, as a consequence, the voltage levels used for accelerated reliability tests have decreased, the BD transient exhibits a marked change in behavior. As the stress voltage is decreased below a threshold value, the BD transient becomes slower. This recently discovered phenomenon has been termed progressive BD, i.e., a gradual growth of the BD spot and of the gate leakage, with a time scale that under operation conditions can be a large fraction of the total time to BD. We review the literature on this phenomenon, describing the current understanding concerning the dependence of the effect on voltage, temperature, oxide thickness, sample geometry, and its physical structure. We also discuss the possible relation to the so-called soft oxide BD mode and propose a simpler, more consistent terminology to describe different BD regimes. The last part of the paper is dedicated to exploratory studies, still at the early stages given the very recent subject, concerning the impact on the BD of materials for the metal-oxide-semiconductor gate stack and, in particular, metal gates.

Breakdown kinetics of Pr2O3 films by conductive-atomic force microscopy

The dielectric breakdown (BD) kinetics of praseodymium thin films has been determined by comparison between current-voltage measurements on large-area (up to 78.54μm2) metal-oxide-semiconductor structures and conductive-atomic force microscopy (C-AFM). C-AFM clearly images the weak BD single spots under constant voltage stresses. The stress time on the single C-AFM tip dot was varied from 2.5×10−3 to 8×10−2s. The density of BD spots, upon increasing the stress time, exhibits an exponential trend. The Weibull slope and the characteristic time of the dielectric BD have been determined by direct measurements at nanometer scale.

Electrical characterization ofhigh-dielectric-constant/SiO2 metal–oxide–semiconductor gate stacks by a conductive atomic force microscope

A conductive atomic force microscope (CAFM) has been used to study, at the nanometrescale, the dependence of the electrical behaviour on the post-deposition annealing temperature(TA) and the dielectric reliability of ultrathinhigh-dielectric-constant/SiO2 MOS gate stacks. It has been observed that for high enoughTA the conduction becomes more inhomogeneous, leading to the formation of leaky spots thatcould be a problem for the integration of these layers in a standard CMOS microelectronicprocess. The CAFM has also revealed that the values of some parameters related to thedielectric reliability, such as the area of the breakdown spot (i.e. a region that haslost its insulating properties owing to electrical stress), are of the same order forSiO2 layers andhigh-dielectric-constant/SiO2 stacks. Moreover, different conduction regimes, which cannot be detected by standardelectrical characterization techniques, have been observed.

Comparison of SiO 2 and HfO 2 /SiO 2 gate stacks electrical behaviour at a nanometre scale with CAFM

The electrical behaviour of a SiO2 gate layer and a HfO2/SiO2 gate stack are studied at the nanometre scale by means of CAFM. The leaky spot (LS) and breakdown (BD) spot sizes, the post BD current-voltage (I-V) characteristics and the topography features have been compared. LS of ∼600–700 nm2 and BD sizes of 1000–3000 nm2 are measured for the SiO2 layer and the HfO2/SiO2 stack. Post BD I-V characteristics reveal that, for SiO2, I-V curves are well grouped and CAFM compliance is always reached for Vgate<0.5 V. For the HfO2/SiO2 stack, I-V curves show very much dispersion, and the Vgate needed to reach the compliance is larger. Therefore, the high-k layer reduces the severity of the BD event. Even so, a few times the HfO2/SiO2 stack BD spots exhibit I-V characteristics as conductive as SiO2 BD spots.

Gate oxide breakdown on nMOSFET cutoff frequency and breakdown resistance

Gate oxide breakdown effect on CMOS RF devices has been examined. The breakdown spot resistance and total gate capacitance of nMOS transistors decrease with stress. The analytical equation of cutoff frequency including the gate oxide breakdown effect is derived. The impact of oxide breakdown on the performance of an LC oscillator is evaluated. The oscillation frequency of the LC oscillator increases with oxide breakdown.

Structure of the oxide damage under progressive breakdown

The I– V characteristics of ultra-thin gate oxides under progressive breakdown (BD) show a common behavior, indicative of well-defined general physical features of the BD spot. Transmission electron microscopy (TEM) observations give some hints about this structure and on this basis we propose a physical model of the post-BD current, which is in good agreement with data.

Influence of Dielectric Breakdown on MOSFET Drain Current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the on drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.

Electrode conditioning characteristics in vacuum under impulse voltage application in non-uniform electric field

In this paper, we quantitatively investigated impulse conditioning mechanism under nonuniform electric field electrodes in a vacuum. A negative standard lightning impulse voltage was applied between rod and plane electrodes whose materials were Cu-Cr, stainless steel and Cu and gap lengths were d=5 and 10 mm, respectively. Experimental results revealed transition of breakdown (BD) sport region on rod electrode and corresponding BD field strength in conditioning process. As a result, we found that BD spot region started at tip of rod electrode and moved to wider region of rod electrode with lower electric field as shots of voltage application increased before saturation of BD voltage. Finally, by analyzing results with an electric field strength, we propose that the conditioning degree along electrode surface distributed directly proportional to electric field distribution under a nonuniform electric field in a vacuum, irrespective of electrode materials

Spatially resolved diagnosis of stress-induced breakdown in oxide dots by in situ conducting atomic force microscopy

We report an investigation on the stress-induced breakdown (BD) in ultrathin oxide grown by atomic force microscopy (AFM oxide). A conducting atomic force microscopy (c-AFM) technique was employed to stress the AFM oxide and examine its BD behavior. It was found that thermal annealing has a strong impact on the dielectric strength of AFM oxide. The stress-induced trap generation probability, Pt, could be reduced by ∼50% after annealing the oxide at elevated temperatures. Such a thermal effect is related to the local structural relaxation and trap state minimization in AFM oxide upon annealing. The spatially resolved current images allow a microscopic diagnosis of the distribution of BD sites: isolated single BD spots and laterally propagated BD areas were observed in an oxide dot. Soft and hard breakdown sites were also distinguished on the current images.

Observation of Localized Breakdown Spots in Thin SiO[sub 2] Films Using Scanning Capacitance Microscopy

Observation of Localized Breakdown Spots in Thin SiO[sub 2] Films Using Scanning Capacitance Microscopy

Breakdown spots of ultra-thin (EOT < 1.5 nm) HfO 2/SiO 2 stacks observed with enhanced—CAFM

In this work, the (gate) current versus (gate) voltage ( I– V) characteristics and the dielectric breakdown (BD) of an ultra-thin HfO 2/SiO 2 stack is studied by enhanced conductive atomic force microscopy (ECAFM). The ECAFM is a CAFM with extended electrical performance. Using this new set up, different conduction modes have been observed before BD. The study of the BD spots has revealed that, as for SiO 2, the BD of the stack leads to modifications in the topography images and high conductive spots in the current images. The height of the hillocks observed in the topography images has been considered an indicator of structural damage.

Simplified tunnelling current calculation for MOS structures with ultra-thin oxides for conductive atomic force microscopy investigations

As charge tunnelling through thin and ultra-thin silicon dioxide layers is regarded as the driving force for MOS device degradation the determination and characterisation of electrically week spots is of paramount importance for device reliability and failure analysis. Conductive atomic force microscopy (C-AFM) is able to address this issue with a spatial resolution smaller than the expected breakdown spot. For the determination of the electrically active oxide thickness in practice an easy to use model with sufficient accuracy and which is largely independent of the oxide thickness is required. In this work a simplified method is presented that meets these demands. The electrically active oxide thickness is determined by matching of C-AFM voltage–current curves and a tunnelling current model, which is based on an analytical tunnelling current approximation. The model holds for both the Fowler–Nordheim tunnelling and the direct tunnelling regime with one single tunnelling parameter set. The results show good agreement with macroscopic measurements for gate voltages larger than approximately 0.5–1 V, and with microscopic C-AFM measurements. For this reason arbitrary oxides in the DT and the FNT regime may be analysed with high lateral resolution by C-AFM, without the need of a preselection of the tunnelling regime to be addressed.

Characterization of breakdown in ultrathin oxides by hot carrier emission

Hot carrier luminescence excited at low voltages across ultrathin gate oxides is used to describe the localized transport during progressive oxide breakdown. The emission identifies the locations of initial breakdown spots in field effect transistors. The transitions from stress-induced leakage currents to reversible breakdown to final breakdown are accompanied by changes in the efficiency of the emission showing an evolution from inelastic to elastic transport.

Effect of N 2 anneal on thin HfO 2 layers studied by conductive atomic force microscopy

The effect of thermal annealing on the electrical properties of thin HfO 2 layers was studied by conductive atomic force microscopy. Based on high resolution (10 nm) current maps it is possible to observe the transition from a homogeneous current distribution for the non-annealed case towards the presence of electrical weak spots in the annealed samples. Although the current density in the weak spots can reach 20 A/cm 2, local I– V curves indicate that not all of them are acting as a real breakdown spot. The weak spots density observed is around 10 10–10 11/cm 2, which represents 5–10% of the scanned area.