Booth Multiplier Research Articles

Design and Evaluation of Multipliers Using Simulated Annealing and Partitioning Approach

Multipliers are widely used in various fields of engineering, and they are considered to have complex designs. The efficient design of multipliers to meet various design requirements is still an active area of research. In this paper, a thermo-inspired metaheuristic called population-based simulated annealing algorithm, for the design of multipliers using four different resource types, is proposed. Metaheuristics suffers from the problem of scalability and non-convergence as the size and complexity of the circuit increase. Four types of partitioning approaches- output, input, input-output and hybrid-output partitioning are proposed to overcome the same. Proposed partitioning approaches have increased the success rate and reduced the time to realize the circuit. The multipliers designed are synthesized on Cadence Genus with 90 nm technology and compared with traditional designs such as Array, Wallace tree, Dadda and Booth multipliers to conclude that metaheuristics are capable of generating near-optimal solutions in terms of power, area and delay.

Design and analysis of leading one/zero detector based approximate multipliers

Approximate multipliers are widely used in error-tolerant applications to improve circuit performance. For signed multiplication, previous approximate Booth multipliers usually have a large relative error with operands around “0”, while approximate leading one detector based (LOD-based) multipliers are not energy-efficient due to the extra preprocessing module. In this paper, a low relative error leading one/zero detector based approximate multiplier (LOZDAM) is proposed for signed multiplication, which dynamically truncates the operands according to the location of their most significant bits for signed complement data. Its accuracy can be configured to suit fault-tolerant applications with different accuracy requirements. A compensation strategy is proposed to reduce the calculation error of LOZDAMs at a low cost. All proposed designs are evaluated in 28nm/0.9 V/TT/25 °C CMOS. Compared with the exact design, the proposed LOZDAM6/7/8/9 with the width of Booth multiplier being 6/7/8/9-bit reduces average power by 64%/43%/33%/21%, with the mean relative error distance by 2.94%/1.46%/0.73%/0.36%, respectively. Case studies of image sharpening and serial Fast Fourier Transform system both show acceptable error and good power/area savings, which verifies the feasibility of our designs. In general, our proposed LOZD-based approximate multipliers achieve both high accuracy and low power.

Approximate Lifting 2-D DWT Hardware Design for Image Encoder of Wireless Visual Sensors

In this paper, a novel approximate hybrid multiplier design is proposed to reduce the data-path width of lifting two-dimensional (2-D) discrete wavelet transform (DWT) especially for wireless visual sensor node applications. The proposed multiplier design takes multiplier operand of size less by 3-bit and calculates full-width outputs with marginal loss of accuracy which is significant. A parallel approximate lifting 2-D DWT structure is derived using the proposed multiplier design. The proposed approximate 2-D DWT structure uses data-path width 9 and 11 for first and second DWT levels and produces reconstructed colour images higher than 70dB peak-signal-to-noise ratio (PSNR). Compared with the existing fractional wavelet transform (FrWT)-based 2-D DWT structures, the proposed structure has a smaller data-path width and free from overhead. The proposed structure has equal or marginally higher on-chip memory requirement than the existing FrWT based 2-D DWT structures, but involves a substantially less area-delay product (ADP) and energy per image (EPI). The ADP and EPI reduction is O(10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ×). Compared with the existing parallel structure based on hybrid approximate radix-4 and radix-8 encoded Booth multiplier, the proposed approximate structure involves nearly 23% less ADP and 22% less EPI and calculates output images with nearly (4 ~ 7)dB higher PSNR.

Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier

In this brief, we present a novel design methodology of cost-effective approximate radix-4 Booth multipliers, which can significantly reduce the power consumption of error-resilient signal processing tasks. In contrast that the prior studies only focus on the approximation of either the partial product generation with encoders or the partial product reductions with compressors, the proposed method considers two major processing steps jointly by forcing the generated error directions to be opposite to each other. As the internal errors are naturally balanced to have zero mean, as a result, the proposed approximate Booth multiplier can minimize the required processing energy under the same number of approximate bits compared to the previous designs. Simulation results on FIR filtering and image classification applications reveal that the proposed approximate Booth multiplier shows the most attractive energy-performance trade-offs, achieving 28% and 34% of energy reduction compared to the exact Booth multiplier, respectively, with negligible accuracy loss.

State-Of-The-Art On Reversible Multiplier Architectures and Its Comparison for Future Quantum Computing

Multiplication is the key crucial operation in realizing digital signal processing (DSP) functions. It is accomplished by using diverse multiplier architectures. Multiplication operation is furthermost basic and normally used action in the central processing unit (CPU). The multiplication operation is the most fundamental and commonly performed activity in the central processing unit (CPU). An efficient multiplier design should have a high speed, small area, and a low power consumption. Compact, efficient multipliers with minimal power dissipation are needed. The proposed paper provides a thorough inspection of multipliers such as the Array multiplier, Booth multiplier, column bypass multiplier, Baugh-Wooley multiplier, and Vedic multiplier based on their operational activities and working, as well as their benefits and limits. A comparison of these multipliers' performance parameters such as speed, area, power consumption, quantum cost, garbage generation and circuit complexity.

Design of approximate Booth multipliers based on error compensation

With the rapid development of the Internet of Things, terminal equipment is greatly restricted in hardware resources and power supply. Therefore, there is an urgent need for new low-power computing units. Aiming at the problem of high power consumption of the arithmetic unit, a low-power approximate Booth multiplier based on complementary error is proposed. Among them, the new Booth encoder will produce positive errors and the approximate Wallace tree structure will produce negative errors. The mutual compensation of the two errors can improve the accuracy of the approximate Booth multiplier to a certain extent. The experimental results show that, compared with the existing multipliers, the proposed approximate Booth multiplier reduces the power consumption by 20.62% and the delay by 14.45%, saving 19.68% of the area. At the same time, its normalized average error distance is better than the existing approximate multiplier. Finally, the results of image filtering verify the practicality of the proposed approximate Booth multiplier.

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks

Approximate computing has emerged as a new paradigm that provides power-efficient and high-performance arithmetic designs by relaxing the stringent requirement of accuracy. Nonlinear functions (such as softmax, rectified linear unit (ReLU), Tanh, and Sigmoid) are extensively used in deep neural networks (DNNs). However, they incur significant power dissipation due to the high circuit complexity. As DNNs are error-tolerant, the design of approximation-linear functions is possible and desired. In this article, the design of an approximate softmax function (AxSF) is proposed. AxSF is based on a double hybrid structure (DHS). AxSF divides the input of the softmax function into two parts for different processing methods. The most significant bits (MSBs) are processed with lookup tables (LUTs) and an exact restoring array divider (EXDr). Taylor’s expansion and a logarithmic divider are used for the less significant bits (LSBs). An improved DHS (IDHS) is also proposed to reduce the hardware complexity. In IDHS, a novel Booth multiplier is utilized for the hybrid scheme to improve the partial product generation and compression, while the truncated implementation is applied to the divider unit. The proposed DHS and IDHS are compared with existing softmax designs. The results show that the proposed approximate softmax design reduces hardware by 48% and delay by 54% while retaining a high accuracy.

Enhanced Design of High Performance Radix-16 Booth Multiplier Using Partial CSD and DA Algorithm

Enhanced Design of High Performance Radix-16 Booth Multiplier Using Partial CSD and DA Algorithm

Efficient transmission of FECG signal using MIMO – OFDM

The extraction of Fetal Electrocardiogram (FECG) during labor or prenatal phases of pregnancy holds significant importance for early prediction of heart abnormalities. The accuracy of the extracted FECG is crucial for effective diagnosis, but the presence of external noises, particularly from the Maternal ECG (MECG), poses a major challenge in obtaining precise information. To address this issue in biomedical data processing, the study employs Finite Impulse Response (FIR) filters using an array multiplier. One notable challenge encountered in this process is the interference caused by external noises, leading to higher delay and power dissipation. In response, a modified High-Performance Multiplier (HPM) based modified booth multiplier is thoroughly reviewed and validated. This modification aims to enhance overall performance and enable high-speed operations in filtering the FECG signals. The effectiveness of these modified multipliers is assessed using ECG signal information collected from the MIT-BIH Arrhythmia Database, comprising 120 samples. In addition to noise filtering, the study explores the validation of Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) transceivers. These transceivers play a crucial role in ensuring the effective transmission of the extracted FECG signals. The research reveals a significant reduction, up to 80.4%, in both area and power dissipation during simulations conducted in Xilinx ISE 9.1 and Cadence Virtuoso. This achievement highlights the potential for improved efficiency and reliability in the processing and transmission of FECG signals, paving the way for advancements in early detection of fetal heart abnormalities.

Design of Accuracy Configurable Booth Multiplier using Sorting based Compressors

Design of Accuracy Configurable Booth Multiplier using Sorting based Compressors

ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration

Cloud AI acceleration has drawn great attention in recent years, as big models are becoming a popular trend in deep learning. Cloud AI runs high-efficiency inference, high-accuracy inference and training, in demand of flexible floating-point (FP)/integer (INT) multiply–accumulation (MAC) support. Many computing-in-memory (CIM) processors have been proposed for efficient AI acceleration. They usually rely on analog CIM techniques that are only suitable for high-efficiency neural network (NN) inference with low-precision INT MAC support. Since cloud AI demands high efficiency, high accuracy, and high flexibility simultaneously, we propose an innovative architecture reconfigurable digital CIM (ReDCIM) that meets all three requirements. We design the first CIM-based cloud AI processor, ReDCIM, which constructs a unified FP/INT pipeline architecture based on exponent pre-alignment and reconfigurable in-memory accumulation. Bitwise in-memory Booth multiplication is proposed to reduce computation on CIM. The fabricated ReDCIM chip achieves a state-of-the-art energy efficiency of 29.2 TFLOPS/W at BF16 and 36.5 TOPS/W at INT8.

Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology

Multipliers are the basic building blocks in various digital signal processing applications such as convolution, correlation, and filters. However, conventional array multipliers, vedic multipliers were resulted in higher area, power, delay consumptions. Therefore, this work is focused on design and implementation of variable width Radix-4 booth multiplier using Data Scaling Technology (DST). The radix-4 modified booth encoding was used in the production of these incomplete items. In accumulation, the bits of the fractional products are added in a parallel manner with decreased stages using a multi-stage carry propagation adder (MSCPA). The simulation demonstrated that the suggested DST-Radix-4 booth multiplier (DST-R4BM) resulted in higher performance in comparison to traditional multiplies in terms of area, delay, and power.

ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design

Approximate computing technique has been adopted in recent years to develop low power design solutions targeted towards error-tolerant applications. Since the accuracy requirements of an application can vary dynamically at run-time, there is a justified need to design reconfigurable approximate circuits with varying power requirements proportional to computational accuracy. In this paper, we have proposed a novel accuracy reconfigurable approximate booth multiplier circuit. The design involves partial error correction through the addition of sign bits in a broken array multiplier. The design space of sign inclusive 16-bit broken array multipliers is thoroughly analyzed to include only non-redundant accuracy modes. The horizontal and vertical breaks introduced in the booth multiplier circuit are controlled using external control signals stored in a ROM. The proposed reconfigurable multiplier achieves significant power savings compared to accurate multiplier circuit and state-of-the-art accuracy configurable multiplier designs.

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

In this paper, a small-area low-power 64-bit integer multiplier is presented, which is suitable for portable devices or wireless applications. To save the area cost and power consumption, an input vector systolic (IVS) structure is proposed based on four 16-bit radix-8 Booth multipliers and a data input scheme is proposed to reduce the number of signal transitions. This structure is similar to a systolic array in matrix multiply units of a Convolutional Neural Network (CNN), but it reduces the number of processing elements by 3/4 concerning the same vector systolic accelerator in reference. The comparison results prove that the IVS multiplier reduces at least 61.9% of the area and 45.18% of the power over its counterparts. To increase the hardware resource utilization, a Transverse Carry Array (TCA) structure for Partial Products Accumulation (PPA) was designed by replacing the 32-bit adders with 3/17-bit adders in the 16-bit multipliers. The experiment results show that the optimization could lead to at least a 6.32% and 13.65% reduction in power consumption and area cost, respectively, compared to the standard 16-bit radix-8 Booth multiplier. In the end, the precise scale of the proposed IVS multiplier is discussed. Benefiting from the modular design, the IVS multiplier can be configured to support sixteen different kinds of multiplications at a step of 16 bits [16b, 32b, 48b, 64b] × [16b, 32b, 48b, 64b].

VLSI implementation of booth multiplier and carry select adder based fir filter design for ECG signal denoising

Over the last two decades, FIR filters have been the subject of intense research. The design of an adder, which is a major building component in circuit design, determines the overall performance of a system. The Finite Impulse Response (FIR) filter has been increasingly popular in signal processing applications in recent years. For signal processing field applications and VLSI systems, many adders are implemented. Signal denoising, as well as the production of an effective multiplier, had never been explained in any of the previous publications. This paper proposes 8 bit booth multipliers for partial products. The design employs the Carry select and Booth techniques. For partial product addition, the Carry Select Adder (CSA) is employed. The architecture of the FIR filter is proposed for operation with Electro Cardiogram (ECG) signal. It's known as CSA-BOOTH FIR, and it's used for denoising. Using the MATLAB application, the ECG signal with noise is sent into the filter. The denoising method is written in Verilog, with the output recorded in a text file. The binary values are read in MATLAB to denoise the signal. The performance of FPGAs and ASICs is evaluated.

Design and Implementation of Low Power, High-Speed Configurable Approximation 8-Bit Booth Multiplier

Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.

VLSI Design and Implementation of Multipliers for DSP Applications

A multiplier is a critical building block found in processors, embedded systems, VLSI applications, application specific integrated circuits, and most DSP applications. Speed, area, and power are the three primary thrust characteristics in VLSI design. Low power and high speed is the desirable characteristic in many applications that can extend the battery's life expectancy and increase the frequency of operation. The goal of this project is to design, implement and analyse the performance of array multipliers, booth multipliers, Wallace tree multipliers, and modified booth multipliers. In this work multipliers with different bit widths are implemented on Spartan 3E FPGA and their performances are analysed. Among these architectures Wallace tree multiplier provides higher speed of operation and consumes lesser power.

VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier

ABSTRACT Rapidly growing technology has increased the demand for digital signal processing applications that are fast and effective in real-time. One of the basic operations frequently required in these applications is the multiplication operation. There is a need to develop a multiplier with high speed, less area, and low power consumption to improve its performance. One of the fastest multiplier circuits is the Radix-4 Booth multiplier. Booth encoder reduces the number of partial products and hence the number of additions. The pipeline scheme is one of the most used designs to accelerate the multiplier performance. In this paper, two designs are presented. The first proposed design aims to reduce the delay of the multiplication operation of a 16 × 16 multiplier. This design uses a pipeline scheme differently by partitioning the input into two parts and overlapping their processing. The second proposed design reduces the multiplier area by applying enhancements in the modified booth encoder circuit. The proposed circuits are synthesized using XILINX ISE 14.7 and realized using ML605 Virtex 6 FPGA board. The first proposed design achieves higher speed, lower power consumption, and less area than the prior design. The second proposed design achieves more area and power consumption reduction.

Minimum signed digit approximation for faster and more efficient convolutional neural network computation on embedded devices

In the era of smart Internet-of-Things, convolutional neural network (CNN) models with low computational overhead are crucial for low-latency applications in resource-constrained embedded devices. The performance and efficiency of multiplication operations play a vital role in accelerating and optimizing CNN computation. In this article, we propose the MA4C technique, which reduces CNN computation overhead by converting a pretrained CNN’s parameters into approximated minimum signed digit (MSD) representations. MSD representation contains fewer non-zero digits on average compared to the binary representation of a number. The proposed scheme approximates the MSD representations by only considering a specified number of most significant digits. The MA4C technique reduces the computational complexity of multipliers by reducing the number of partial sums. The proposed MSD approximation was applied on various DNN models, and their performance was analyzed for different datasets, varying CNN depth, and network configuration. Implementation of our proposed method on FPGA reduced the logic circuits and multiplier latency by up to 4.2× and 1.2× respectively compared to an 8-bit Booth multiplier for most CNN models.

Correction to: FPGA Design of a Variable Step-Size Variable Tap Length Denlms Filter with Hybrid Systolic-Folding Structure and Compressor-Based Booth Multiplier for Noise Reduction in Ecg Signal

Correction to: FPGA Design of a Variable Step-Size Variable Tap Length Denlms Filter with Hybrid Systolic-Folding Structure and Compressor-Based Booth Multiplier for Noise Reduction in Ecg Signal