Approximate Lifting 2-D DWT Hardware Design for Image Encoder of Wireless Visual Sensors

Abstract

In this paper, a novel approximate hybrid multiplier design is proposed to reduce the data-path width of lifting two-dimensional (2-D) discrete wavelet transform (DWT) especially for wireless visual sensor node applications. The proposed multiplier design takes multiplier operand of size less by 3-bit and calculates full-width outputs with marginal loss of accuracy which is significant. A parallel approximate lifting 2-D DWT structure is derived using the proposed multiplier design. The proposed approximate 2-D DWT structure uses data-path width 9 and 11 for first and second DWT levels and produces reconstructed colour images higher than 70dB peak-signal-to-noise ratio (PSNR). Compared with the existing fractional wavelet transform (FrWT)-based 2-D DWT structures, the proposed structure has a smaller data-path width and free from overhead. The proposed structure has equal or marginally higher on-chip memory requirement than the existing FrWT based 2-D DWT structures, but involves a substantially less area-delay product (ADP) and energy per image (EPI). The ADP and EPI reduction is O(10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ×). Compared with the existing parallel structure based on hybrid approximate radix-4 and radix-8 encoded Booth multiplier, the proposed approximate structure involves nearly 23% less ADP and 22% less EPI and calculates output images with nearly (4 ~ 7)dB higher PSNR.