VLSI implementation of booth multiplier and carry select adder based fir filter design for ECG signal denoising

Abstract

Over the last two decades, FIR filters have been the subject of intense research. The design of an adder, which is a major building component in circuit design, determines the overall performance of a system. The Finite Impulse Response (FIR) filter has been increasingly popular in signal processing applications in recent years. For signal processing field applications and VLSI systems, many adders are implemented. Signal denoising, as well as the production of an effective multiplier, had never been explained in any of the previous publications. This paper proposes 8 bit booth multipliers for partial products. The design employs the Carry select and Booth techniques. For partial product addition, the Carry Select Adder (CSA) is employed. The architecture of the FIR filter is proposed for operation with Electro Cardiogram (ECG) signal. It's known as CSA-BOOTH FIR, and it's used for denoising. Using the MATLAB application, the ECG signal with noise is sent into the filter. The denoising method is written in Verilog, with the output recorded in a text file. The binary values are read in MATLAB to denoise the signal. The performance of FPGAs and ASICs is evaluated.