Design and analysis of leading one/zero detector based approximate multipliers

Abstract

Approximate multipliers are widely used in error-tolerant applications to improve circuit performance. For signed multiplication, previous approximate Booth multipliers usually have a large relative error with operands around “0”, while approximate leading one detector based (LOD-based) multipliers are not energy-efficient due to the extra preprocessing module. In this paper, a low relative error leading one/zero detector based approximate multiplier (LOZDAM) is proposed for signed multiplication, which dynamically truncates the operands according to the location of their most significant bits for signed complement data. Its accuracy can be configured to suit fault-tolerant applications with different accuracy requirements. A compensation strategy is proposed to reduce the calculation error of LOZDAMs at a low cost. All proposed designs are evaluated in 28nm/0.9 V/TT/25 °C CMOS. Compared with the exact design, the proposed LOZDAM6/7/8/9 with the width of Booth multiplier being 6/7/8/9-bit reduces average power by 64%/43%/33%/21%, with the mean relative error distance by 2.94%/1.46%/0.73%/0.36%, respectively. Case studies of image sharpening and serial Fast Fourier Transform system both show acceptable error and good power/area savings, which verifies the feasibility of our designs. In general, our proposed LOZD-based approximate multipliers achieve both high accuracy and low power.