Bondwire Inductor Research Articles

Compact LTCC band pass filter using high‐Q bondwire inductor for RF system‐in‐package applications

AbstractA low‐temperature cofired ceramics(LTCC)‐embedded bandpass filter (BPF) using a high quality (Q) factor (130) bondwire inductor is proposed for radio frequency (RF) system‐in‐package (SiP) applications. The usage of high‐Q bondwire inductors significantly improves the passband insertion loss (1.35 dB) compared with that (2.0 dB) of embedded spiral inductors at 5.25 GHz and also greatly reduces the device size to 1.000 × 1.500 × 0.675 mm3. The insertion loss and the size of the proposed bondwire filter are the best compared with those of open literature filters. Excellent tolerances of 1.9% and 4.4% are, respectively, measured for the cutoff frequency and the insertion loss. We expect the proposed bondwire filter play an important role to improve the performance and to reduce the sizes of RF SiP circuits. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 1424–1428, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24390

ESD-Protected Wideband CMOS LNAs Using Modified Resistive Feedback Techniques With Chip-on-Board Packaging

A novel modified resistive feedback structure for designing wideband low-noise amplifiers (LNAs) is proposed and demonstrated in this paper. Techniques including feedback through a source follower, an <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R-C</i> feedback network, a gate peaking inductor inside the feedback loop, and neutralization capacitors are used. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Two LNAs, LNA1 and LNA2, were fabricated using a TSMC digital 90-nm CMOS technology. Both chips were tested on board using chip-on-board packages with ESD diodes added at the inputs and outputs. LNA1 achieves a 3-dB bandwidth of 9 GHz with 10 dB of power gain and a minimum noise figure (NF) of 4.2 dB. LNA2 achieves a 3-dB bandwidth of 3.2 GHz with 15.5 dB of power gain and a minimum NF of 1.76 dB. The two LNAs have third-order intermodulation intercept points of 8 and 9 dBm. Their power consumptions are 20 and 25 mW with a 1.2-V supply, respectively.

On-Chip Bondwire Magnetics with Ferrite-Epoxy Glob Coating for Power Systems on Chip

A novel concept of on-chip bondwire inductors and transformers with ferrite epoxy glob coating is proposed to offer a cost effective approach realizing power systems on chip (SOC). We have investigated the concept both experimentally and with finite element modeling. A Q factor of 30–40 is experimentally demonstrated for the bondwire inductors which represents an improvement by a factor of 3–30 over the state-of-the-art MEMS micromachined inductors. Transformer parameters including self- and mutual inductance and coupling factors are extracted from both modeled and measured S-parameters. More importantly, the bondwire magnetic components can be easily integrated into SOC manufacturing processes with minimal changes and open enormous possibilities for realizing cost-effective, high-current, high-efficiency power SOCs.

Integrated RF Interference Suppression Filter Design Using Bond-Wire Inductors

Design techniques are presented for the realization of high-performance integrated interference suppression filters using bond-wire inductors. A new configuration is proposed for mitigating the impact of mutual coupling between the bond wires. A differential low-noise amplifier with an integrated on-chip passive interference suppression filter is designed at 2.1 GHz in a 0.18-mum CMOS process, and achieves a transmit leakage suppression of 10 dB at 190-MHz offset. The differential filter uses metal-insulator-metal capacitors and bond-wire inductors and occupies only 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The cascaded system achieves a measured gain of 9.5 dB with a 1.6-dB noise figure and -5 dBm out-of-band IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and consumes 11 mA from a 2-V supply.

Low phase noise bond wire VCO for DVB‐H

AbstractA low phase noise VCO with bond wire inductor for DVB‐H is implemented in TSMC CMOS 0.18 μm. The bond wire VCO exhibits −137 dBc/Hz at 1 MHz with the 5 mA current consumption. To meet the DVB‐H phase noise requirement, bond wire modeling is introduced in this paper. Due to the bond wire characteristics, Q value of the VCO inductor is more than 25 at 1 GHz. The proposed wire bond inductor provides an additional frequency tuning option after IC fabrication by modifying the length of the wire bond. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 859–863, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23228

A CMOS Active Balun Using Bond Wire Inductors and a Gain Boosting Technique

An active balun with a single-ended input and a pair of differential outputs is presented for the input stages of differential circuits. The active balun, which is composed of an input resonator and cascaded common-gate amplifiers, was implemented using 0.18-mum CMOS technology and bond wire inductors. A body-source cross-coupled configuration was used to enhance the gain of the active balun. The gain is 9.3 dB at 1.8 GHz, and the phase and the amplitude error are less than 2deg and 1 dB, respectively, in the frequency range of 1 to 2 GHz, even for a P1dB of -2.7 dBm. The balun consumes 9 mA for 3-V supply voltage.

2.14-GHz 대역 고효율 Class-F 전력 증폭기 개발

본 논문에서는 Freescale사의 Si-LDMOSFET 4-W 소자를 이용하여 고효율 class-F 전력 증폭기를 구현하였다. Class-F 전력 증폭기를 구현하는데 있어서 모든 하모닉 성분들에 대해 원하는 임피던스를 갖도록 조정하기는 불가능하기 때문에 2차와3차 하모닉 성분만을 조율하여 회로의 간결함과 동시에 상대적으로 높은 효율을 얻을 수 있었다. 또한, 본 논문에 설계된 증폭기는 보다 정확하게 하모닉 성분을 조율하기 위해, LDMOSFET의 대신 호 등가 모델에서 가장 큰 영향을 미치는 drain-source capacitance(Cds)와 bonding inductance(Lb)를 추출하여 하모닉 조율 회로를 설계하였다 제작된 고효율 class-F 전력 증폭기의 측정 결과 drain-efficiency(DE) 65.1%, power-added-efficiency(PAE) 60.3%의 효율을 얻을 수 있었다. We have implemented a highly efficient 2.14-GHz class-F amplifier using Freescale 4-W peak envelope power(PEP) RF Si lateral diffusion metal-oxide-semiconductor field effect transistor(LDMOSFET). Because the control of the all harmonic contents is very difficult, we have managed only the <TEX>$2^{nd}\;and\;3^{rd}$</TEX> harmonics to obtain the high efficiency with simple harmonic control circuit. In order to design the harmonic control circuit accurately, we extracted the bonding wire inductance and drain-source capacitance which are dominant parasitic and package effect components of the device. And then, we have fabricated the class-F amplifier. The measured drain and power-added efficiency are 65.1 % and 60,3 %, respectively.

Integrated Inductors for RF Transmitters in CMOS/MEMS Smart Microsensor Systems

This paper presents the integration of an inductor by complementary metal-oxide-semiconductor (CMOS) compatible processes for integrated smart microsensorsystems that have been developed to monitor the motion and vital signs of humans invarious environments. Integration of radio frequency transmitter (RF) technology withcomplementary metal-oxide-semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize the wireless smart microsensors system. Theessential RF components such as a voltage controlled RF-CMOS oscillator (VCO), spiralinductors for an LC resonator and an integrated antenna have been fabricated and evaluatedexperimentally. The fabricated RF transmitter and integrated antenna were packaged withsubminiature series A (SMA) connectors, respectively. For the impedance (50 ) matching,a bonding wire type inductor was developed. In this paper, the design and fabrication of thebonding wire inductor for impedance matching is described. Integrated techniques for theRF transmitter by CMOS compatible processes have been successfully developed. Aftermatching by inserting the bonding wire inductor between the on-chip integrated antennaand the VCO output, the measured emission power at distance of 5 m from RF transmitterwas -37 dBm (0.2 μW).

Modeling of electromagnetically coupled substrate noise in flash a/d converters

A new method for modeling the electromagnetically coupled substrate noise from digital gates in large mixed-signal integrated circuits was developed. The unique feature of the method is that it employs a modular approach to model noise coupling via current injection from the digital gates which alleviates the problems associated with the current methodology in so far as the circuit size, instability the effects of parasitics and the accuracy issues are concerned. The method was demonstrated on the characterization of the substrate noise issues in FLASH analog-to-digital (A/D) converters. The model was then used to study the addition of the p/sup +/ guards around the input devices of comparators in order to asses their effectiveness in reducing the substrate noise. The effect of variations in the package bond-wire inductances in the net injected current noise was also modeled.

Characterisation of substrate noise in flash A/D converters

A method for modelling electromagnetically coupled substrate noise in mixed signal integrated circuits was developed. This method was then used to characterise the substrate noise issues in FLASH analogue to digital (A/D) converters. The model was also used to study the addition of the P+ guards around the input devices of the comparators in order to assess their effectiveness in reducing the substrate noise. Finally, the effect of variations in the package's bond wire inductances in the net injected current noise was modelled.

A bond-wire inductor-MOS varactor VCO tunable from 1.8 to 2.4 GHz

This paper presents a technique that optimizes LC-tank CMOS voltage-controlled oscillators (VCOs) by minimizing the product of phase noise and power consumption. Moreover, it shows that the minimum depends on the tank's quality factor Q, the device noise coefficient /spl gamma/, and the ratio between the maximum oscillation amplitude and supply voltage /spl alpha/. Prototypes, realized in a 0.35-/spl mu/m process, show the following performances: -122.5 dBc/Hz at 600 kHz from a 1.9-GHz carrier, with 2-V supply voltage and 1-mA current consumption. The VCO can be tuned between 1.8-2.4 GHz, when the varactor control voltage is varied between 0-3.5 V. In the proposed realization, the tank is made of a metal-oxide-silicon varactor (operated between accumulation and deep depletion) and a bond-wire inductor, realized connecting two pads to a package frame lead to be compatible with the production environment.

An Approach to Linear Scalable DH-PHEMT Model for Millimeterwave Application

This paper describes a scalable small-signal equivalent circuit for 0.25 μm gatelength Double Heterojunction delta-doped PHEMTs. The scaling rules for all elements except the pad capacitances and bondwire inductances have been determined. Good agreement is obtained between simulation results and measured results for 2 times 20 μm , 2 times 40 μm, 2 times 60 μm, 2 times 100 μm gate width (number of gate fingers times unit gate width) DH PHEMT.

A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS

This paper presents a transceiver that uses a 4-bit flash analog-to-digital converter (ADC) for the receiver and an 8-bit current-steering digital-to-analog converter (DAC) for the transmitter. The 8-GSamples/s converters are 8-way time interleaved. Digital compensation reduces the input offset of the ADC comparators to less than 0.6 LSB, improves the accuracy of the interleaved sampling clocks to within 10 ps, and reduces systematic coupling noise to less than 18 mV on the 800-mV signal swing. 1.1-nH bondwire inductors distribute the parasitic capacitances at the transceiver input and output, reducing attenuation by 10 dB at 4 GHz. Equalization algorithms using the converters compensate for the 1.5-GHz transceiver bandwidth to allow 8-GSamples/s multilevel data transmission.

A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors

This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-/spl mu/m CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively.

Fully Integrated Low Phase-Noise VCOs: From Special Processing to Standard CMOS

An overview is given on the several options for and problems associated with creating high-quality integrated inductors for VCOs. Special processing techniques are reported that can enhance the performance of a normal planar inductor coil. Bonding Wire inductors are presented as an alternative, that allows state-of-the-art phase noise performance at no extra cost. Finally, it is shown that by thorough analysis of standard planar inductors with finite-element simulations, performances can be achieved that are even better than structures requiring extra processing cost. This is done despite a low-ohmic substrate with only two metal layers.

Microwave MEMS-based voltage-controlled oscillators

A microwave voltage-controlled oscillator (VCO) based on coupled bonding wire inductors and microelectromechanical system (MEMS)-based variable capacitors for frequency tuning is demonstrated in this paper. The MEMS-based variable capacitors were fabricated in a standard polysilicon surface micromachining technology. The variable capacitors have a nominal capacitance of 1.4 pF and have a Q factor of 23 at 1 GHz and 14 at 2 GHz. The capacitance is variable from 1.4 to 1.9 pF as the tuning voltage is swept from 0 to 5 V. The VCO, fabricated in a 0.5 /spl mu/m CMOS technology, was assembled in a ceramic package where MEMS and CMOS dice were bonded together. The oscillator operates at 2.4 GHz, achieves a phase noise of -122 dBc/Hz at 1 MHz offset from the carrier, and exhibits a tuning range of 3.4%.

Experimental study of the spatially-modulated light detector

Usually, integrated detectors in CMOS exhibit long recovery times, limiting the detector bandwidth to only a few MHz. This is due to the long absorption length and the slow diffusion speed of photo-generated carriers. Different approaches have been proposed to solve these problems hereby taxing the compatibility with standard CMOS fabrication processing. We present a novel detector for high-speed light detection in standard CMOS. To solve the problem of slow CMOS-detector recovery, the incident light is spatially modulated and the spatially modulated component of the photo-generated carrier distribution is measured. Though only a single light input signal is required, from the detector on, analog signal processing can be achieved fully differentially. Subsequently, expected good PSRR (Power supply rejection ratio) allows integration with digital circuits. Avoiding hybridization eliminates the conventional problems caused by bonding-pad capacitance, bonding-wire inductance. This reduces the associated signal degradation. In addition, the very low detector capacitance, due to the low effectively used detector area and the low area capacitance of the n-well junction, yields high voltage readout of the detector. This facilitates further amplification and conversion to digital signal levels. The detector will be applicable in arrays due to expected low cross talk. The expected fields of operation involve: serial and parallel optical communication receivers (e.g. for WDM), DVD-reading heads with integrated amplifier, etc. First measurements show 200 Mbit/s operation with a detector-responsivity of 0.05 A/W at λ=860 nm and 0.132 A/W at λ=635 nm. The detector has inherently a low capacitance, in this case only 50 fF (for an effective detector area of 70×70 μm 2).

Low Power Down-Conversion RF Mixers Based on the Gilbert Cell Approach

Three down-conversion mixers for low-voltage, balanced 900 MHz wireless applications are introduced. The mixers are implemented in a 0.8 μm BiCMOS process and based on the four transistor BJT switching quad widely used in Gilbert cells. The mixers are designed to operate at a supply voltage of 1.5 V and without external components. The implemented mixers have a few decibels of conversion loss, a third-order input intercept point of a few dBm and a single sideband noise figure of about 15 dB. It is demonstrated that modest mixer operation performance is achieved with a DC power consumption of only 1 mW. Also planar inductors on silicon and bond-wire inductors are shown to be valuable to achieve a return loss of about 9 dB for input and output ports of a mixer. The measurement results for the mixers as well as the lumped element models for the used planar inductor and for the bondwire are presented.

A 1-GHz bipolar class-AB operational amplifier with multipath nested Miller compensation for 76-dB gain

A 1-GHz operational amplifier with a gain of 76 dB while driving a 50-/spl Omega/ load is presented. The equivalent input noise voltage is as low as 1.2 nV//spl radic/Hz. This combination of extremely high bandwidth, high gain, and low noise is the result of a three-stage all-n-p-n topology combined with a multipath nested Miller compensation. Using 10-GHz f/sub T/ n-p-n transistors, the realizable bandwidth could be of the order of 2-3 GHz. However, bond-wire inductances restrict the useful bandwidth to 1 GHz. The amplifier occupies an active area of 0.26 mm/sup 2/ and has been realized in the bipolar part of a 1-/spl mu/m BiCMOS process.

15 Gbit/s silicon bipolar amplifier IC using a novel mounting technique

A DC-coupled silicon bipolar amplifier IC, for operation in future multigigabit optical communication systems, has been fabricated using ≥30 GHz double-polysilicon transistors. Using a novel HF-connection technique for reducing the bondwire inductance, we have succeeded in the fabrication of a 14 dB gain amplifier IC, with a flatness better than ±0.5 dB, combined with a –3 dB bandwidth of 12.8 GHz. This is the highest bandwidth ever reported for a bonded amplifier circuit in any semiconductor technology.