Large diameter, dislocation-free Ge single crystalline wafers are relatively new in the semiconductors industry. In the past a few groups reported on the use of 200 mm Ge wafers for manufacturing of germanium-on-insulator (GeOI) substrates [1-3], with an oxide bonding interface, while oxide-free, electrically conductive Si-Ge wafer bonding was not addressed so far. Finally, by using Si wafers this type of bond can be used e.g. for high-efficient multi-junction solar cells and high-electron-mobility transistor (HEMT) [4,5].First the manufacturing of high quality 200 mm diameter Ge wafers was addressed. For the wafer bonding processes standard silicon wafers were bonded to germanium wafers in order to fabricate oxide-free bonds. The wafer bonding process was performed using the EVG ComBond® system: first the native oxides from both wafer surfaces were removed using ion beam sputtering process, followed by the transfer of both wafers in ultra-high vacuum (UHV) to the bonding process station. In order to prevent thermally induced stress due to the different thermal expansion coefficients the bonding process is performed at room temperature (RT).The goal of this work was to demonstrate the feasibility of the bonding process, so main focus was on mechanical and morphological analysis of the surfaces and of the bonded interfaces. Atomic force microscopy (AFM) and spectroscopic ellipsometry (SE) were used to determine the surface roughness and oxide thickness, respectively. Both parameters are crucial for successful RT Si-Ge wafer bonding. The high quality results and the bonding energy were revealed using scanning acoustic microscopy (SAM) measurements as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy (X-TEM) showed a bonding interface with an about 2.2 nm thin amorphous layer and no additional oxygen concentration (see Figure 1). In order to enhance the visibility of the oxygen and argon distributions measured with energy dispersive x-ray spectroscopy (EDXS) the detected element intensities are expressed qualitatively. Figure 1. X-TEM (left) and qualitative EDXS line scan (right) of the Si-Ge bonding interface. Here 100% represents the maximum detected intensity of each element. The work reported here is a first step in developing wafer bonding processes e.g. for solar cells fabrication using large diameter Si and Ge wafers. Future work will focus on bonding process optimization and electrical characterization of the bonded interfaces.[1] C. Deguet et al ., “Fabrication and characterisation of 200 mm germanium-on-insulator (GeOl) substrates made from bulk germanium,” in El. Let., vol. 42, no. 7, pp. 51-52 (2006).[2] T. Akatsu et al., “200mm germanium-on-insulator (GeOI) by Smart CutTM technology and recent GeOI pMOSFETs achievements,” in 2005 IEEE Int. SOI Conf. Proc. (2005): 137-138.[3] C.J. Tracy et al., “Germanium-on-insulator substrates by wafer bonding,” in Journal of El. Mat. 33, 886–892 (2004).[4] O. Höhn et al., ”Development of Germanium-Based Wafer-Bonded Four-Junction Solar Cells,” in IEEE Journal of Photovoltaics, vol. 9, no. 6, pp. 1625-1630 (2019).[5] W. Rachmady et al., “300mm Heterogeneous 3D Integration of Record Performance Layer Transfer Germanium PMOS with Silicon NMOS for Low Power High Performance Logic Applications,” in 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, pp. 29.7.1-29.7.4 (2019). Figure 1