Bipolar Action Research Articles

Raised Source/Drain Dopingless Junctionless Accumulation Mode FET: Design and Analysis

We design and analyze a raised source/drain dopingless junctionless accumulation mode FET (RDJAMFET) on an intrinsic silicon film using charge plasma concept. This device does not have any physical doping or junctions. Using 2-D simulations, we demonstrate that by making use of the physical design parameters, the device can achieve reduced band-to-band tunneling-induced parasitic bipolar transistor action in the off-state as compared with the planar dopingless junctionless FET (DJFET) for sub-20-nm channel length devices. Further, the RDJAMFET has better gate control and shows significant improvements in terms of drain-induced barrier lowering, subthreshold swing, and $I_{\mathrm{\scriptscriptstyle ON}}$ / $I_{\mathrm{\scriptscriptstyle OFF}}$ as compared with the DJFET for sub-20-nm channel length devices.

Controlling L-BTBT and Volume Depletion in Nanowire JLFETs Using Core–Shell Architecture

In this paper, we propose the use of a p+ core in the core–shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) in n-NW junctionless FETs (NWJLFETs). We show that the lateral band-to-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p+ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) of $\sim 10^{7}$ even for a channel length of 7 nm.

Optimization of 1700V 4H-SiC JBS Diode Parameters

The in-depth design optimization of the active layer of the 1700V class 4H-SiC JBS/MPS diode structure is discussed. The important design parameters such as junction depth (d), width (w) of p+ areas, and spacing (s) between them were optimized for the best possible trade-off between the unipolar ON-state voltage drop, the OFF-state breakdown voltage, and the bipolar surge current capability. The optimization was performed using a state-of-the-art simulator using device models calibrated on a commercially available JBS rectifier. The results show that the spacing s between the p+ regions is the most decisive parameter which has to be properly designed according to the required voltage class. For the 1700 V voltage class, s should be between 2 to 4 μm and the s/w ratio should be kept low. The depth d of the p+ pattern has a pronounced impact on the ignition of bipolar action such that with decreasing d the surge current capability decreases significantly.

On a Parasitic Bipolar Transistor Action in a Diode ESD Protection Device

In this work, we show that an excessive lattice heating problem can occur in the diode electrostatic discharge (ESD) protection device connected to a VDD bus in the popular diode input protection scheme, which is favorably used in CMOS RF ICs. To figure out the reason for the excessive lattice heating, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-D device simulator. We analyze the simulation results in detail to show out that a parasitic pnp bipolar transistor action relating nearby p+-substrate contacts is responsible for the excessive lattice heating in the diode protection device, which has never been focused before anywhere.

Tunneling-triggered bipolar action in junctionless tunnel field-effect transistor

We analyse a novel hybrid semiconductor field-effect transistor (FET), known as the junctionless tunnel FET (JL-TFET). We show that a parasitic bipolar transistor action, which is highly undesirable in conventional metal/oxide/semiconductor FETs and junctionless transistors, is the mechanism that activates the JL-TFET ON state. It is found that the sub-threshold slope (SS) in the JL-TFET is strongly dependent on the silicon thickness and a sub-60 mV/decade SS is observed for a thin silicon body only. We further study the JL-TFET design parameters as regards the effects of the control gate workfunction, P-gate workfunction, and isolation region on the JL-TFET characteristics.

A study of bipolar control action with EMPC for the position control of DC motors

The paper studies the use of bipolar control action with experience mapping based prediction controller (EMPC) for the position control of DC motors. EMPC is based on the human learning mechanism without any need for a detailed mathematical plant model. Experiential learning is used in EMPC to control and adapt to environmental changes introducing robustness. An improved method for the development of experiences to achieve faster settling times is presented. A new concept of control action in EMPC to achieve faster response named ‘bipolar action’ is presented. The advantages of bipolar action are studied in terms of the transient response characteristics and adaptation to changes in system parameters. The performance of EMPC using bipolar action is compared against the use of unipolar action and also against the popular MRAC for position control for changes in active load torque, motor terminal voltage and armature resistance. A new method of correcting the control action by sampling the system response during the initial phase to reduce the overshoots in systems where overshoots are not tolerated is presented. EMPC with bipolar action is practically implemented and the results are provided and compared with the simulation results.

In vitro assessment of induced phrenic nerve cryothermal injury.

Phrenic nerve injury, both left and right, is considered a significant complication of cryoballoon ablation for treatment of drug-refractory atrial fibrillation, and functional recovery of the phrenic nerve can take anywhere from hours to months. The purpose of this study was to focus on short periods of cooling to determine the minimal amount of cooling that may terminate nerve function related to cryo ablation. Left and/or right phrenic nerves were dissected from the pericardium and connective tissue of swine (n = 35 preparations). Nerves were placed in a recording chamber modified with a thermocouple array. This apparatus was placed in a digital water bath to maintain an internal chamber temperature of 37°C. Nerves were stimulated proximally with a 1-V, 0.1-ms square wave. Bipolar compound action potentials were recorded proximal and distal to the site of ablation both before and after ablation, then analyzed to determine changes in latency, amplitude, and duration. Temperatures were recorded at a rate of 5 Hz, and maximum cooling rates were calculated. Phrenic nerves were found to elicit compound action potentials upon stimulation for periods up to 4 hours minimum. Average conduction velocity was 56.7 ± 14.7 m/s preablation and 49.8 ± 16.6 m/s postablation (P = .17). Cooling to mild subzero temperatures ceased production of action potentials for >1 hour. Taking into account the data presented here, previous publications, and a conservative stance, during cryotherapy applications, cooling of the nerve to below 4°C should be avoided whenever possible.

New concepts of sofosbuvir-based treatment regimens in patients with hepatitis C

<h3>ABSTRACT</h3> Adhesion-type G protein-coupled receptors (aGPCRs) participate in a vast range of physiological processes. Correspondingly, these receptors are associated with diverse human diseases, such as developmental disorders, defects of the...

Effect of Emitter Layer on the Signal Generation of the Active Pixel Sensor

The image sensor in the optical mouse reads the scene of the bottom, and compares it with the last sceneto acquire the moving data. The scene should be read with high frame rate to make the moving of the cursor soft and exact. The high frame rate means the short time to integrate the signal charge. The weak signal causes malfunctioning of the moving of the cursor. The signal should be amplified to ensure the signal to noise ratio. Some type of the pixel in the optical mouse uses a bipolar transistor to amplify the signal. The conventional bipolar transistor used in the optical mouse has full covering emitter layer on the base layer. The emitter layer helps the bipolar action, but it decreases the signal electron-hole pair generation since the generation occurs in the collector-base junction. We propose the emitter structure which covers only the boundary of the base layer. The photo current of the new structure increased 20% compared to the conventional structure.

High-Gain Multiple-Gate Photodetector With Nanowires in the Channel

A design of a photodetector with multiple gates and a modified channel, incorporating silicon nanowires, is proposed, and its performance is modeled. Working under lateral bipolar action, the gate/channel geometry increases the device photocurrent in the accumulation mode and leads to photoresponsivities of greater than .

A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins—Write/Read Assist Techniques for 1-V Operated Memory Cells

The use of multiple power supplies with different output voltages has a great advantage in that it makes it possible to realize high performance ULSIs with low power dissipation. This paper presents a high-speed low-power SRAM that employs three power supplies (1, 2, and 3.3 V). A 1-V power supply is mainly used in the SRAM core to save standby and/or active power, while a 2-V supply is used in critical components to realize high performance. The voltage applicable to each MOSFET is up to 2.2 V because of the use of a 5-nm ultrathin gate oxide, and so the 3.3-V power supply is used only for LV-TTL level I/O buffers. Secure write operation for 1-V six-transistor memory cells is guaranteed by using a new switched powerline impedance scheme. To reduce dynamic write power dissipation, a segmented bitline scheme is adopted and long global bitlines are assigned to the 4th (topmost) metal layer. The data stored in memory cells are read out via virtual-GND lines by sensing the change in current volume. The practical use of parasitic bipolar action in SOI MOSFETs is being actively considered as a way of obtaining a large read current from memory cells. In addition, a 1-V double-rail bidirectional intradatabus is developed for transferring multibit high-speed data between the SRAM core and I/O buffers. A 32K-word × 9-bit SRAM chip, fabricated with the 0.2-μm-gate CMOS/SIMOX process, has achieved a 7.5-ns address access time for 65-pF external loads. The power dissipation during standby is less than 0.3 mW and the values for 100-MHz operation are 5.8 mW (write) and 11.0 mW (read), excluding that of the 3.3-V I/O buffers.

Extended-$\hbox{p}^{+}$ Stepped Gate LDMOS for Improved Performance

In this brief, we propose a new extended-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> stepped gate (ESG) thin-film silicon-on-insulator laterally double-diffused metal-oxide-semiconductor (LDMOS) with an extended-p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> - p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> junction instead of an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -p junction, thus delaying the parasitic bipolar junction transistor action. The stepped gate structure enhances RESURF in the drift region and minimizes the gate-drain capacitance. Based on 2-D simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed, and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.

The Characteristics of n- and p-Channel Poly-Si Thin-Film Transistors with Fully Ni-Salicided S/D and Gate Structure

n- and p-channel poly-Si thin-film transistors with fully Ni-self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate structure (n- and p-channel FUSA-TFTs) have been successfully fabricated on a thick channel layer. The conventional poly-Si gate is replaced by the fully Ni-silicided gate, and the parasitic S/D resistance of the FUSA-TFTs is significantly reduced by the fully Ni-silicided S/D structure. The fully Ni-salicidation process is executed at a low temperature of for a short rapid thermal annealing time. Experimental results show that the FUSA-TFTs give increased on/off current ratio, improved subthreshold characteristics, less threshold voltage roll-off, lower parasitic S/D resistance, higher gate capacitance, and larger field-effect mobility than conventional TFTs. The FUSA-TFTs effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FUSA-TFTs are suitable for three-dimensional integration applications and high performance driver circuits in the active-matrix liquid crystal displays.

Long-Range Lateral Dopant Diffusion in Tungsten Silicide Layers

Novel diode test structures have been manufactured to characterize long-range dopant diffusion in tungsten silicide layers. A tungsten silicide to p-type silicon contact has been characterized as a Schottky barrier rectifying contact with a silicide work function of 4.8 eV. Long-range diffusion of boron for an anneal at 900degC for 30 min has been shown to alter this contact to become ohmic. Long-range diffusion of phosphorus with a similar anneal alters the contact to become a bipolar n-p diode. Bipolar diode action is demonstrated experimentally for anneal schedules of 30 min at 900deg C, indicating long-range diffusion of phosphorus ( ~ 38 mum). SIMS analysis shows dopant redistribution is adversely affected by segregation to the silicide/oxide interface. The concept of conduit diffusion has been demonstrated experimentally for application in advanced bipolar transistor technology.

Latch-up effects in CMOS inverters due to high power pulsed electromagnetic interference

Latch-up effects in two stage cascaded CMOS digital inverters due to high power pulsed electromagnetic interference, are reported. Latch-up was observed to occur at and above 25.5 dB m of pulsed interference at frequencies of 1.23 GHz and 4 GHz. When a latch-up event occurred, the devices failed to respond to the input logic signal even after the pulsed interference was removed. Devices required to be reset to return to normal operation. Latch-up for pulsed interference at the higher frequency of 4 GHz occurred at higher power levels, indicating a suppression of the interference effects at higher frequencies due to the by-pass path effects provided by the intrinsic device capacitances. High power interference induced excess carriers and the corresponding body currents that activated the parasitic bipolar transistor action were found to play a key role in triggering the latch-ups, and are proposed here as the main mechanism for the upsets. The parasitic resistances R1 and R2 for the cascaded inverters were calculated to be 4.3 and 2.8 kΩ, respectively, and the corresponding excess body currents triggering the latch-ups were 0.163 and 0.25 mA, respectively.

A Modified Dickson Charge Pump Circuit with High Efficiency and High Output Voltage

A power-efficient Dickson-based charge pump circuit is proposed and verified in this paper. Using a PMOS transfer switch in the new circuit solves the problem of the output voltage loss and its body control switch can suppress the parasitic bipolar action. Comparing this new one with the conventional circuit, the new circuit generates output voltage as high as 2.9VDD while the conventional one only 2VDD. For their efficiency values, the new circuit has better efficiency than the conventional one by as much as 14.5% with the area overhead of 12.2% using 3.5-μm and 40-V CMOS high-voltage process.

Physical Model of Noise Mechanisms in SOI and Bulk-Silicon MOSFETs for RF Applications

The noise mechanisms at high frequencies in MOSFETs are analyzed and an analytical model is presented for devices operating at gigahertz frequencies. The proposed model is applied to floating body silicon-on-insulator (SOI) as well as bulk-silicon MOS transistors and experimentally verified. The model accounts for the mechanisms of 1) channel thermal noise; 2) shot-noise due to impact ionization; and 3) substrate back-gate-coupled thermal noise. Compact, closed-form analytical expressions of the noise power spectral density and the minimum noise figure (NF) are presented. At the same technology level, the experimental data and the model show that SOI MOSFETs are able to attain lower NF than bulk-silicon devices by reduction of the back-gate transconductance. However, the higher drain electric field in the SOI, and the parasitic bipolar action and floating body enhance impact-ionization-associated shot-noise, which becomes the limiting noise mechanism at drain voltages higher than the drain onset voltage of ldquokinkrdquo effect. A correlation between the onset voltage and the DC electrical characteristics is shown.

High Soft-Error Tolerance Body-Tied Silicon-on-Insulator Technology with Partial Trench Isolation

This paper presents soft-error tolerance for partially depleted silicon-on-insulator (SOI) devices with partial trench isolation (PTI) that realize a body-tied structure. Mechanism of charge collections due to alpha-particle strikes is clarified for a body-tied SOI device with the PTI structure and a body-floating SOI device. It is estimated that the soft-error tolerance of the body-floating SOI device is lower than that of the body-tied one because of parasitic bipolar action. Soft-error testing by using 0.18 µm 4 Mbit static random-access memory (SRAM) indicates that the body-tied SOI devices with the PTI structure have high soft-error tolerance as compared with bulk devices. The charge collections for the PTI structure are also investigated to mitigate the soft errors. It is demonstrated that the body-tied PTI SOI technology is one of the best solutions for high-performance system LSIs with high soft-error tolerance.

A Novel Feature of Neutron-Induced Multi-Cell Upsets in 130 and 180 nm SRAMs

Bit-multiplicity of neutron-induced single event upsets (SEU) in CMOS SRAMs formed with 130 and 180 nm technologies was analyzed using mono-energetic, quasi-mono-energetic, and spallation neutron sources in various accelerator facilities. The energy dependence of the ratio of multi-cell upsets (MCUs) to the total number of upsets can be described by a Weibull-type function with the threshold energy of the MCU. The 130 nm SRAMs show a novel feature of multi-cell upsets (MCUs) including frequency distribution of the multiplicity of error bits. In the case of the 130 nm SRAM, the probability function of the MCU can be expressed as a sum of exponential and Lorentzian functions of the multiplicity of error bits. According to previous results of 3-dimensional device simulation, the Lorentzian component can be due to bipolar action.

P‐27: Anomalous Increased Drain Current Characteristics of a‐Si:H TFTs with Long Channel Width

AbstractA‐Si:H TFTs having channel widths ranging from 40 μm to 48,000 μm were successfully fabricated and investigated for characterization of electrical dependence on channel width. TFTs with a critical channel width larger than 10,000 μm show width‐normalized drain current increases significantly even at the low lateral electrical field of 1.9 MV/m. for a critical bias condition, width‐normalized drain current has the dependency on channel width, resulting from the increased field effect mobility from 0.722 cm2/V‐sec to 1.6 cm2/V‐sec at VGS=12 V due to the dissipated power at the drain edge and the NPN bipolar action.