Abstract
This paper presents soft-error tolerance for partially depleted silicon-on-insulator (SOI) devices with partial trench isolation (PTI) that realize a body-tied structure. Mechanism of charge collections due to alpha-particle strikes is clarified for a body-tied SOI device with the PTI structure and a body-floating SOI device. It is estimated that the soft-error tolerance of the body-floating SOI device is lower than that of the body-tied one because of parasitic bipolar action. Soft-error testing by using 0.18 µm 4 Mbit static random-access memory (SRAM) indicates that the body-tied SOI devices with the PTI structure have high soft-error tolerance as compared with bulk devices. The charge collections for the PTI structure are also investigated to mitigate the soft errors. It is demonstrated that the body-tied PTI SOI technology is one of the best solutions for high-performance system LSIs with high soft-error tolerance.
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