Binary Multiplication Research Articles

Conception of efficient key-dependent binary diffusion matrix structures for dynamic cryptographic algorithms

The existing static cryptographic algorithms suffer from different performance and security challenges. These limitations are attributed to their fixed structure, where the substitution and diffusion primitives maintain the same values throughout the process. In this paper, we present a new framework of a dynamic binary diffusion matrix with flexible dimensions (n×n). The proposed solution replaces the static diffusion primitives, in existing symmetric and un-keyed cryptographic algorithms, with dynamic primitives. We define six different dynamic and flexible binary diffusion forms, four that are invertible, and two that are non-invertible, and hence, they could be used for different security services. However, using a single diffusion form does not always guarantee the required cryptographic properties. To that effect, we propose a binary multiplication scheme of a dynamic primary matrix and its transposed form, which yields the desired efficiency, and provides good resistance against recent implementation attacks, yet without degrading the system performance. We conduct security and performance analyses to validate the effectiveness of the proposed solution. The results confirm the cryptographic performance in terms of the linear branch number and the number of fixed points. In this context, the best-obtained branch number is 4 for n=8 and 5 for n=12 for the invertible forms, while for the non-invertible ones, the best branch number is 3 for n=8 and 4 for n=12. Moreover, in terms of the number of fixed points, the obtained numbers are very close to 0 for the invertible and non-invertible forms.

Design of Power Efficient Posit Multiplier using Compressor Based Adder

Abstract: Posit number system has been used in many applications, especially the deep learning. Because of how well its nonuniform number distribution aligns with deep learning's data distribution, deep learning's training process can be sped up. The hardware multiplier is typically built with the widest mantissa bit-width available due to the flexibility of posit numbers' bitwidth. Such multiplier designs consume a lot of power since the mantissa bit-width is not necessarily the maximum value. This is especially true when the mantissa bit-width is tiny. The mantissa multiplier is still built to have the widest bit-width feasible, but it is broken into numerous smaller multipliers. At run-time, just the necessary tiny multipliers are turned on. The regime bitwidth, which can be used to determine the mantissa bit-width, controls those smaller multipliers. This design technique is applied to 8-bit, 16-bit, and 32-bit posit formats.

Scalable set of reversible parity gates for integer factorization

Classical microprocessors operate on irreversible gates, that, when combined with AND, half-adder and full-adder operations, execute complex tasks such as multiplication of integers. We introduce parity versions of all components of a multiplication circuit. The parity gates are reversible quantum gates based on the recently introduced parity transformation and build on ground-space encoding of the corresponding gate logic. Using a quantum optimization heuristic, e.g., an adiabatic quantum computing protocol, allows one to quantum mechanically reverse the process of multiplication and thus factor integers, which has applications in cryptography. Our parity approach builds on nearest-neighbor constraints equipped with local fields, able to encode the logic of a binary multiplication circuit in a modular and scalable way.

COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC

The rapid progress in quantum computing has initiated a new round of cryptographic innovation, that is, developing postquantum cryptography (PQC) to resist attacks from well-established quantum computers. In this brief, we propose a novel compact and optimized polynomial multiplier accelerator (COPMA) for high-performance implementation of learning-with-rounding (LWR)-based PQC. As not many LWR-based PQC schemes are available in the literature, we have just used Saber, the National Institute of Standards and Technology (NIST) third-round PQC standardization finalist, as a typical case study example. First of all, we have formulated the polynomial multiplication, the major component of Saber, into a novel “subpolynomial”-based processing format for compact computation (yet has the potential for fast operation). Then, we have designed the proposed algorithm into an area-efficient polynomial multiplication hardware accelerator with high-frequency operational capability. Finally, we have verified the efficiency of the developed COPMA and have deployed it to build a cryptoprocessor. The implementation and analysis demonstrate the superior performance of the proposed COPMA. The proposed strategy is highly efficient and can be extended to build other PQC hardware accelerators.

A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA

This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over GF(2233) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels.

Quantum Binary Field Multiplication with Optimized Toffoli Depth and Extension to Quantum Inversion

The Shor's algorithm can find solutions to the discrete logarithm problem on binary elliptic curves in polynomial time. A major challenge in implementing Shor's algorithm is the overhead of representing and performing arithmetic on binary elliptic curves using quantum circuits. Multiplication of binary fields is one of the critical operations in the context of elliptic curve arithmetic, and it is especially costly in the quantum setting. Our goal in this paper is to optimize quantum multiplication in the binary field. In the past, efforts to optimize quantum multiplication have centred on reducing the Toffoli gate count or qubits required. However, despite the fact that circuit depth is an important metric for indicating the performance of a quantum circuit, previous studies have lacked sufficient consideration for reducing circuit depth. Our approach to optimizing quantum multiplication differs from previous work in that we aim at reducing the Toffoli depth and full depth. To optimize quantum multiplication, we adopt the Karatsuba multiplication method which is based on the divide-and-conquer approach. In summary, we present an optimized quantum multiplication that has a Toffoli depth of one. Additionally, the full depth of the quantum circuit is also reduced thanks to our Toffoli depth optimization strategy. To demonstrate the effectiveness of our proposed method, we evaluate its performance using various metrics such as the qubit count, quantum gates, and circuit depth, as well as the qubits-depth product. These metrics provide insight into the resource requirements and complexity of the method. Our work achieves the lowest Toffoli depth, full depth, and the best trade-off performance for quantum multiplication. Further, our multiplication is more effective when not used in stand-alone cases. We show this effectiveness by using our multiplication to the Itoh-Tsujii algorithm-based inversion of F(x8+x4+x3+x+1).

Novelty for Different Prime Partial Bi-Ideals in Non-Commutative Partial Rings and Its Extension

In computer programming languages, partial additive semantics are used. Since partial functions under disjoint-domain sums and functional composition do not constitute a field, linear algebra cannot be applied. A partial ring can be viewed as an algebraic structure that can process natural partial orderings, infinite partial additions, and binary multiplications. In this paper, we introduce the notions of a one-prime partial bi-ideal, a two-prime partial bi-ideal, and a three-prime partial bi-ideal, as well as their extensions to partial rings, in addition to some characteristics of various prime partial bi-ideals. In this paper, we demonstrate that two-prime partial bi-ideal is a generalization of a one-prime partial bi-ideal, and three-prime partial bi-ideal is a generalization of a two-prime partial bi-ideal and a one-prime partial bi-ideal. A discussion of the mpb1,(mpb2,mpb3) systems is presented. In general, the mpb2 system is a generalization of the mpb1 system, while the mpb3 system is a generalization of both mpb2 and mpb1 systems. If Φ is a prime bi-ideal of ℧, then Φ is a one-prime partial bi-ideal (two-prime partial bi-ideal, three-prime partial bi-ideal) if and only if ℧\Φ is a mpb1 system (mpb2 system, mpb3 system) of ℧. If Θ is a prime bi-ideal in the complete partial ring ℧ and Δ is an mpb3 system of ℧ with Θ∩Δ=ϕ, then there exists a three-prime partial bi-ideal Φ of ℧, such that Θ⊆Φ with Φ∩Δ=ϕ. These are necessary and sufficient conditions for partial bi-ideal Θ to be a three-prime partial bi-ideal of ℧. It is shown that partial bi-ideal Θ is a three-prime partial bi-ideal of ℧ if and only if HΘ is a prime partial ideal of ℧. If Θ is a one-prime partial bi-ideal (two-prime partial bi-ideal) in ℧, then HΘ is a prime partial ideal of ℧. It is guaranteed that a three-prime partial bi-ideal Φ with a prime bi-ideal Θ does not meet the mpb3 system. In order to strengthen our results, examples are provided.

Implementation of ALU Using Modified Radix-4 Modified Booth Multiplier

Abstract: In this project, we propose a novel multiplier hardware design based on a radix - 4 modified booth encoder. The standard modified Booth encoding (MBE) provides an uneven partial product array due to the extra partial product bit at the least significant bit position of each partial product row. In this brief, a simple technique for constructing a regular partial product array with fewer partial product rows and low overhead is provided, reducing the complexity of partial product reduction as well as the space, time, and power of MBE multipliers. A SPST-based adder is examined and designed for the reduction of power in partial product reduction

Real-time high-precision FMCW laser range extraction method based on a hardware multiplier array.

Frequency-modulated continuous wave (FMCW) laser interferometry is an ideal large-scale absolute distance measurement method. It has advantages of high precision and noncooperative target measurement capability, with no blind spot for ranging. To meet the requirements of high-precision, high-speed 3D topography measurement technologies, a faster measurement speed of FMCW LiDAR at each measurement point is required. To solve the shortcomings of the existing technology, a real-time high-precision hardware solution method (including but not limited to FPGA and GPU) for lidar beat frequency signals is provided here based on hardware multiplier arrays to reduce lidar beat frequency signal processing time and to save energy and resource consumption during processing. A high-speed FPGA architecture was also designed for the frequency-modulated continuous wave lidar range extraction algorithm. The whole algorithm was designed and implemented in real time based on the principle of full-pipelines and parallelism. The results show that the processing speed of the FPGA system is faster than that of current top-performing software implementations.

A Characterization of Associative Evolution Algebras

Evolution algebras are non-associative in general, that is, the binary multiplication law is not associative. However, there exist some of them that are associative. In this paper we deal with these last ones. We give an explicit classification of these algebras and show that the concept of associativity is equivalent to the existence of an unitary element for non-degenerate evolution algebras. We also explicitly describe the derivation space of these algebras.

Highly Accurate and Energy Efficient Binary-Stochastic Multipliers for Fault-Tolerant Applications

Stochastic circuits use randomly distributed bitstreams to represent numbers, so leading to small areas and low power dissipation. However, it does not only result in a long latency and thus increases energy, but also reduces computing accuracy. In this brief, a design of parallel stochastic multipliers with high accuracy and low energy is proposed. To this end, an algorithm for finding optimal multiplicative bitstreams (OpMulbs) is developed for multipliers. Experimental results show that the proposed parallel multipliers using OpMulbs are the most accurate among currently available stochastic multipliers. They also require much less energy with a smaller latency, compared to the others. With a mean squared error of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.02{\times } 10^{-6}$ </tex-math></inline-formula> , the proposed 8-bit multiplier shows a 42.18%, 48.15%, 20.35%, and 55.56% reduction in area, power, latency, and energy, respectively, compared to an 8-bit exact binary multiplier. The applications in multiply-accumulate units and image processing algorithms show that the proposed multipliers outperform the state-of-the-art stochastic designs in several considered criteria and binary designs in hardware cost.

Binary operations on neuromorphic hardware with application to linear algebraic operations and stochastic equations

Non-von Neumann computational hardware, based on neuron-inspired, non-linear elements connected via linear, weighted synapses—so-called neuromorphic systems—is a viable computational substrate. Since neuromorphic systems have been shown to use less power than CPUs for many applications, they are of potential use in autonomous systems such as robots, drones, and satellites, for which power resources are at a premium. The power used by neuromorphic systems is approximately proportional to the number of spiking events produced by neurons on-chip. However, typical information encoding on these chips is in the form of firing rates that unarily encode information. That is, the number of spikes generated by a neuron is meant to be proportional to an encoded value used in a computation or algorithm. Unary encoding is less efficient (produces more spikes) than binary encoding. For this reason, here we present neuromorphic computational mechanisms for implementing binary two’s complement operations. We use the mechanisms to construct a neuromorphic, binary matrix multiplication algorithm that may be used as a primitive for linear differential equation integration, deep networks, and other standard calculations. We also construct a random walk circuit and apply it in Brownian motion simulations. We study how both algorithms scale in circuit size and iteration time.

Design and application of memristor hybrid logic circuit

To address the large area and high power consumption issues in traditional integrated circuits, an improved design of nanoscale memristor is used to realize the adder and multiplier in digital logic circuits. The OR and AND gates of the memristor's MRL structure are used to design the XOR and XNOR logic gates of the 2T-4M structure. A full adder is created by combining these logic gates with CMOS, where the CMOS inverter improves signal drive. By improving the 2T-4M structure, a new 2T-4M logic module is implemented, and a 2-bit binary multiplier is designed based on this module. LTspice simulation ensures that the circuit design is correct. When compared to the previously reported MRL full adder and 2-bit binary multiplier, the full adder significantly reduced the number of components, improved the delay time by 53.3$%$, and reduced power consumption by 1.93 mW. The 2-bit binary multiplier design also has some advantages in terms of total component count, requiring only 18 in total. Finally, a full adder is used to create an encrypted array circuit to encrypt and decrypt the image, proving the circuit's feasibility in practical application.

Design and optimization of MSI-enabled multi-precision binary multiplier architecture

Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113-bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of floating-point computation. Notably, it enhances throughput by accommodating the multiplication of multiple batches of inputs with each operation initiation, surpassing existing binary multiplication systems. A unique Mantissa Similarity Investigation (MSI) implementation is developed and integrated into the binary multiplier architecture. Comparative analysis of the path delay in 24-bit mode against existing 24-bit multipliers demonstrates that the novel MSI-interfaced binary multiplier architecture, with and without MSI, exhibits reduced path delay compared to all existing systems, as anticipated.

High-Speed Grouping and Decomposition Multiplier for Binary Multiplication

In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications.

Device‐System End‐to‐End Design of Photonic Neuromorphic Processor Using Reinforcement Learning

AbstractThe incorporation of high‐performance optoelectronic devices into photonic neuromorphic processors can substantially accelerate computationally intensive matrix multiplication operations in machine learning (ML) algorithms. However, the conventional designs of individual devices and system are largely disconnected, and the system optimization is limited to the manual exploration of a small design space. Here, a device‐system end‐to‐end design methodology is reported to optimize a free‐space optical general matrix multiplication (GEMM) hardware accelerator by engineering a spatially reconfigurable array made from chalcogenide phase change materials. With a highly parallelized integrated hardware emulator with experimental information, the design of unit device to directly optimize GEMM calculation accuracy is achieved by exploring a large parameter space through reinforcement learning algorithms, including deep Q‐learning neural network, Bayesian optimization, and their cascaded approach. The algorithm‐generated physical quantities show a clear correlation between system performance metrics and device specifications. Furthermore, physics‐aware training approaches are employed to deploy optimized hardware to the tasks of image classification, materials discovery, and a closed‐loop design of optical ML accelerators. The demonstrated framework offers insights into the end‐to‐end and co‐design of optoelectronic devices and systems with reduced human supervision and domain knowledge barriers.

A Novel Multiplier Hardware Organization for Finite Fields Defined by All-One Polynomials

In this brief, a novel, energy-efficient hardware organization for a finite-field multiplier based on irreducible all-one polynomials (AOPs) is proposed. The proposed AOP multiplier organization deploys three distinct submodules, which constitute a left-shifting network (reduction), an AND network (multiplication), and a three-input XOR tree (accumulation). Previously reported state-of-the-art implementation distributes these operations to systolic arrays, which are elegant in layout but do not yield the most efficient solution. The advantages of the proposed organization compared with those reported in the literature include reduced cost and power dissipation for a given clock frequency constraint (or increased clock frequency for a given power constraint) and the absence of bypassing problems due to fewer pipeline stages. Both the previously reported and the proposed organizations have been implemented in Verilog for three different binary-field sizes using the TSMC 90 nm standard cell library and have been synthesized for three distinct frequency targets using Cadence Genus Synthesis tool. The proposed organization achieves 18%, 31%, and 19% reduction in average leakage, dynamic capacitance, and area, respectively, compared with state-of-the-art schemes and thus can be considered for energy-efficient, compact portable systems, including wireless sensors.

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2&amp;times;2, 3&amp;times;3, 4&amp;times;4, 5&amp;times;5, and 6&amp;times;6. We use these cells to build 8&amp;times;8, 16&amp;times;16, 32&amp;times;32, 64&amp;times;64, and 128&amp;times;128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3&amp;times;3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

Editorial

Dear Readers, It gives me great pleasure to announce the eighth regular issue of 2022. In this issue, various topical aspects of computer science are covered by 18 authors from 5 countries in 5 articles. As always, I would like to thank all the authors for their sound research and the editorial board for their highly valuable review effort and suggestions for improvement. These contributions, together with the generous support of the consortium members, sustain the quality of our journal. In an ongoing effort to further strengthen our journal, I would like to expand the editorial board: If you are a tenured associate professor or above with a strong publication record, you are welcome to apply to join our editorial board. We are also interested in receiving high-quality proposals for special issues on new topics and trends. Please consider yourself and encourage your colleagues to submit high-quality articles or special issue proposals for our journal. In this regular issue, I am very pleased to introduce the following 5 accepted articles: Raoua Abdelkhalek, Imen Boukhris, and Zied Elouedi from Tunisia present their research on more trustworthy predictions based on the uncertain framework of belief function theory to support the representation, quantification and management of imperfect evidence. In a research collaboration between Jordan and the USA, Abd Al-Rahman Al-Nounou, Osama Al-Khaleel, Fadi Obeidat, and Mohammad Al-Khaleel present a methodology for designing binary multipliers, in which different sizes of customized partial products generation cells are designed and used as smaller building blocks. Venilton FalvoJr, Anderson da Silva Marcolino, Nemesio Freitas Duarte Filho, Edson OliveiraJr, and Ellen Francine Barbosa present the design, development and experimental evaluation of a software product line for mobile learning applications. Ghazala Hcini, Imen Jdey, and Hela Ltifi from Tunesia introduce their research on a new and robust deep learning model for automatically classifying malaria cells as infected or uninfected, built on a convolutional neural network. And last but not least, Sercan Yal&amp;ccedil;&amp;#305;n, Musa E&amp;#351;it, and Mehmet &amp;#304;shak Y&amp;uuml;ce from Turkiye discuss their approach to estimating climatological parameters based on artificial intelligence techniques with particle swarm optimization and deep neural networks.

PLAM: A Posit Logarithm-Approximate Multiplier

The Posit Number System was introduced in 2017 as a replacement for floating-point numbers. Since then, the community has explored its application in Neural Network related tasks and produced some unit designs which are still far from being competitive with their floating-point counterparts. This paper proposes a Posit Logarithm-Approximate Multiplication (PLAM) scheme to significantly reduce the complexity of posit multipliers, the most power-hungry units within Deep Neural Network architectures. When comparing with state-of-the-art posit multipliers, experiments show that the proposed technique reduces the area, power, and delay of hardware multipliers up to 72.86%, 81.79%, and 17.01%, respectively, without accuracy degradation.