Design and application of memristor hybrid logic circuit

Abstract

To address the large area and high power consumption issues in traditional integrated circuits, an improved design of nanoscale memristor is used to realize the adder and multiplier in digital logic circuits. The OR and AND gates of the memristor's MRL structure are used to design the XOR and XNOR logic gates of the 2T-4M structure. A full adder is created by combining these logic gates with CMOS, where the CMOS inverter improves signal drive. By improving the 2T-4M structure, a new 2T-4M logic module is implemented, and a 2-bit binary multiplier is designed based on this module. LTspice simulation ensures that the circuit design is correct. When compared to the previously reported MRL full adder and 2-bit binary multiplier, the full adder significantly reduced the number of components, improved the delay time by 53.3$%$, and reduced power consumption by 1.93 mW. The 2-bit binary multiplier design also has some advantages in terms of total component count, requiring only 18 in total. Finally, a full adder is used to create an encrypted array circuit to encrypt and decrypt the image, proving the circuit's feasibility in practical application.