BiCMOS Circuits Research Articles

A low-power wide-dynamic-range analog VLSI cochlea

Low-power wide-dynamic-range systems are extremely hard to build. The biological cochlea is one of the most awesome examples of such a system: It can sense sounds over 12 orders of magnitude in intensity, with an estimated power dissipation of only a few tens of microwatts. In this paper, we describe an analog electronic cochlea that processes sounds over 6 orders of magnitude in intensity, and that dissipates 0.5 mW. This 117-stage, 100 Hz to 10 KHz cochlea has the widest dynamic range of any artificial cochlea built to date. The wide dynamic range is attained through the use of a wide-linear-range transconductance amplifier, of a low-noise filter topology, of dynamic gain control (AGC) at each cochlear stage, and of an architecture that we refer to as overlapping cochlear cascades. The operation of the cochlea is made robust through the use of automatic offset-compensation circuitry. A BiCMOS circuit approach helps us to attain nearly scale-invariant behavior and good matching at all frequencies. The synthesis and analysis of our artificial cochlea yields insight into why the human cochlea uses an active traveling-wave mechanism to sense sounds, instead of using bandpass filters. The low power, wide dynamic range, and biological realism make our cochlea well suited as a front end for cochlear implants.

Performance optimization of BiCMOS circuits under reduced supply voltage

Performance optimization of BiCMOS circuits under reduced supply voltage

Performance optimization of BiCMOS circuits under reduced supply voltage

As the supply voltage is reduced, the speed superiority of BiCMOS over CMOS may be diminished, but BiCMOS still has the advantage of inducing relatively smaller characteristic degradation in nMOS transistors by suppressing the drain voltage in the gate. Introducing a new quantitative methodology to evaluate hot electron-induced degradation of nMOS transistor characteristics, this report finds that both BiNMOS gates and CBiMOS gates will have a considerable superiority over CMOS gates in the voltage range from 2.5 V to 3.3 V, even with the same nMOS transistor characteristics. BiNMOS is 30% faster than CMOS owing to amplification of the pMOS drain current by an npn transistor. CBiCMOS is 40% faster and has a sevenfold longer life than CMOS. The speed improvement comes from amplification of both pMOS and nMOS drain currents by npn and pnp transistors, respectively, and the lifetime improvement is due to the effect of the voltage drop through the pnp transistors on the drain terminal of the nMOS transistors. The analytical methodology was also utilized to choose an optimum drain structure, although CMOS necessitates the LDD (lightly doped drain), SD (single drain) structure. Thus, the speed of the gates can be further improved, and the speed of CBiCMOS is expected to be 45% faster than that of CMOS gates. Even in the case of SD structure, the lifetime of CBiCMOS was estimated to be two orders of magnitude longer than that of CMOS with LDD structure. © 1998 Scripta Technica. Electr Eng Jpn, 121(4): 56–64, 1997

Modelling and testing for bridging faults in CMOS and BiCMOS combinational circuits

Transistor level models and testing methodologies are developed for detecting the bridging faults in CMOS and BiCMOS circuits. The quiescent power supply current (IDDQ) is utilized as the basis of modelling and test generation. Multiple and single bridging faults are covered. Modelling and testing techniques are presented. The first technique employs a new model called the Current Transfer Function (CTF) that is used to detect the bridging faults in CMOS and BiCMOS circuits. The CTF is a Boolean representation of the IDDQ flow path in terms of input variables and transistor topology of a circuit. The other technique employs an extension of the logic transistor function (LTF) model that was developed earlier for detection of transistor stuck faults. This technique is used for modelling and generating the test for single bridging faults in CMOS circuits, as it is simpler and efficient. However, because of certain limitations this technique is not extended for bridging faults in BiCMOS circuits and the multiple bridging faults in CMOS circuits. The CTF and LTF are automatically generated by the path algebra technique.

A precise transient model for delayed input BiCMOS digital circuits

A detailed methodology to perform the transient analysis of digital BiCMOS circuits is presented. The analysis takes into account high level injection effects, the capacitances at the base, and short-channel effects for the MOS drain current. The model is general and its equations are derived for delayed input signals. The effect of the input slew rate on the gate delay is evaluated. The various correlations between the device/circuit parameters and the overall delay performance are examined. The model predictions show excellent agreement with HSPICE simulated delay.

Low-power BiCMOS circuits for high-speed interchip communication

A universal BiCMOS low-voltage-swing transceiver (driver/receiver) with low on-chip power consumption is reported. Using a 3.3 V supply, the novel transceiver can drive/receive signals from several low-voltage-swing transceivers with termination voltages ranging from 5 V down to 2 V and frequencies well above 1 GHz. Measured results of test circuits fabricated in 0.8-/spl mu/m BiCMOS technology are also presented.

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

Although BiCMOS technology has been used to realize high-speed cache memories, the unscalable 0.8 V Vbe of the bipolar makes it difficult to design 1.5 V BiCMOS circuits including bipolar sense amplifiers. Four circuits in a 0.3 /spl mu/m 4 Mb BiCMOS SRAM overcome this difficulty: (1) boost-BinMOS gates for address decoding, (2) an optimized word-boost for a highly-resistive-load memory cell, (3) a stepped-down CML cascoded bipolar sense amplifier, (4) optimum boost-voltage generator. The SRAM has 6 ns access time at a minimum supply voltage, 1.5 V.

Temperature-compensated linear BiCMOS transconductor

A BiCMOS circuit technique for realising temperature-compensated linear transconductors is described which uses two linear MOS transconductors and a bipolar translinear current gain cell. The theory of operation is presented and simulation results are used to verify theoretical predictions. The results show that the transconductance can be varied over three decades and its temperature coefficient is <200 ppm//spl deg/C.

Differential BiCMOS logic circuits: fault characterization and design-for-testability

Merged Current Switch Logic (MCSL) and Differential Cascode Voltage Switch Logic (DCVSL) are two common structures for differential BiCMOS logic family, that have several potential applications in high-speed VLSI circuits. This paper studies the fault characterization of these BiCMOS circuits. The impact of each possible single defect on the behavior of the circuits is analyzed by simulation. A new class of faults which is unique to differential circuits is identified and its testability is assessed. We propose a design-for-testability method that facilitates testing of this class of faults. Two different realizations for this method are introduced. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated. >

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 /spl mu/m BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Open faults in BiCMOS gates

Opens in BiCMOS structures are analyzed here. It is shown that some opens cannot be detected by stuck-fault or other functional tests, since some transistors in BiCMOS gates do not affect the logical function of the gate. A switch-level model for CMOS circuits is extended to include bipolar devices. With this switch-level model, opens that cannot be detected by stuck-faults or other functional tests are easily identified. It is also shown that, in BiCMOS circuits, an open defect in one transistor can accelerate the wearout of another nondefective transistor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Novel high speed circuit structures for BiCMOS environment

Novel high speed BiCMOS circuits including ECL/CMOS, CMOS/ECL interface circuits and a BiCMOS sense amplifier are presented. A generic 0.8 /spl mu/m complementary BiCMOS technology has been used in the circuit design. Circuit simulations show superior performance of the novel circuits over conventional designs. The time delays of the proposed ECL/CMOS interface circuits, the dynamic reference voltage CMOS/ECL interface circuit and the BiCMOS sense amplifier are improved by 20, 250, and 60%, respectively. All the proposed circuits maintain speed advantage until the supply voltage is scaled down to 3.3 V. >

Analysis of BiCMOS buffer for input voltages with finite rise time

A BiCMOS digital logic gate is analyzed for input voltages with a finite rise or fall time. A new gate delay model to account for the input slope is developed. A set of accurate yet simple closed-form delay expressions are derived for the first time in terms of the input signal slew rate as well as circuit and device parameters. SPICE simulations are used to verify the accuracy of the analytical delay model. The BiCMOS circuit is characterized in terms of the input slew rate, the fan-in, fan-out, and the circuit delay constants. The model can be incorporated in timing simulators and timing analyzers for BiCMOS ULSI circuit design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V/sub DD/. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 /spl mu/m BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Highly testable design of BiCMOS logic circuits

Most of the work reported in the literature to date on the testability of BiCMOS circuits has concentrated on fault characterization and the need for a suitable testing method that can address the peculiarities of BiCMOS circuits. The problem of adequately testing large BiCMOS logic networks remains open and complex. In this paper, we introduce a new design for testability technique for BiCMOS logic gates that results in highly testable BiCMOS logic circuits. The proposed design incorporates two features: a test charge/discharge path and built-in current sensing (BICS). The test charge/discharge path is activated only during testing and facilitates the testing of stuck-open faults using single test vectors. BICS facilitates testing of faults that cause excessive IDDQ. HSPICE simulation results show that the proposed design can detect stuck-open faults at a test speed of 10 MHz. Faults causing excessive IDDQ are detected by BICS with a detection time of 1 ns and a settling time of 2 ns. Impact of the proposed design on normal operation is minimal. The increase in propagation delay in normal operation is less than 3%. This compares very favorably with CMOS BICS reported in the literature, where the propagation delay increase was 20%, 14.4% respectively. The increase in the area is less than 15%. >

A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays

Proposes an optimization procedure for the bipolar base doping profile for a high-speed BiCMOS circuit. This procedure aims to achieve the minimum propagation delay time, taking the power supply, the load capacitance, and the bipolar device layout into consideration. For a small load capacitance, the peak base doping concentration and the base width should be as small as possible. However, for a high load capacitance, the optimized base doping profile can vary under the emitter area constraint. Utilizing this optimization procedure, it will be shown that the propagation delay time can be reduced by more than 30% at the same MOS current (I/sub MOS/=1 mA) through the coordinated reduction of both the vertical doping profile and the horizontal dimensions of the bipolar transistor, with the power supply voltage scaled from 5 to 3.3 V. >

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-/spl mu/m BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor. >

Schottky merged BiCMOS structures

A new merged BiCMOS structure is presented. It incorporates a Schottky diode between the base and the collector of the n-p-n bipolar transistor. The structure offers the same reduced area advantage of merged over conventional BiCMOS, and is shown to have granted latchup immunity to BiCMOS circuits. The device simulations using HSPICE verify the latchup immunity. >

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS &amp; BiCMOS Circuits

The logic behavior and performance of ECL gates under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage, e.g., 79% for ECL versus 54% for BiCMOS and 69% for CMOS equivalent gates. Performance degradation faults such as delay, current and Voltage Transfer Characteristics (VTC) or Noise Margin (NM) faults are analyzed as applied to these gates. It is shown that logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates (around 95%). However, for equivalent ECL gates to attain a fault coverage of around 98%, both logical and NM fault testing have to be used.

Analysis of resistive bridging fault detection in BiCMOS digital ICs

This paper presents a study of the effects on the electrical behavior of BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the static and dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering different testing techniques (current monitoring, functional, and delay testing). Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection of bridging faults in BiCMOS circuits is more difficult than in the CMOS case when functional or delay testing is used whereas it becomes more effective when adopting current monitoring. >