BiCMOS Circuits Research Articles

TCAD Modeling for Si–Ge HBT THz Detectors

Terahertz (THz) response of transistor and integrated circuit yields important information about device parameters and has been used for distinguishing between working and defective transistors and circuits. Using a TCAD model for SiGe HBTs we simulate their current-voltage characteristics and their response to sub-THz (300\,GHz) radiation. Applying different mixed mode schemes in TCAD, we simulated the dynamic range of the THz response for SiGe HBTs and showed that it is comparable with that of the TeraFET detectors. The HBT response to the variations of the detector design parameters are investigated at different frequencies with the harmonic balance simulation in TCAD. These results are useful for the physical design and optimization for the HBT THz detectors and for the identification of faulty SiGe HBT and Si BiCMOS circuits using sub-THz or THz scanning.

(Invited) Integration of an Epitaxial-Base-Link HBT Device with fT = 300GHz, fmax 480GHz in 90nm CMOS

SiGe HBT based BiCMOS technologies have found widespread use in millimeter-Wave (mmW) applications such as high-speed communication and automotive radar, but are also receiving increased attention for operating frequencies above 100GHz. The drive for higher operating frequencies while reducing power consumption continues to fuel the development of new BiCMOS technologies with HBTs featuring higher switching speeds (fmax) integrated with smaller, more power efficient and cost effective CMOS nodes. There is strong evidence however, that in volume production double poly self-aligned (DPSA) HBT architectures may be limited to fmax of 400GHz[i],[ii],[iii],[iv],[v],[vi]. Alternative HBT architectures to overcome this limitation have been proposed[vii],[viii],[ix].In this paper we report the successful integration of a SiGe HBT module with fT = 300GHz, fmax = 480GHz in a 90nm BiCMOS technology platform. Building on previous studies by IHP[x] and Infineon[xi] the Epitaxial-Base-Link process flow was further adapted for compatibility to the 90nm CMOS base technology. The new technology platform features seven Cu metal layers high quality passives including a TaN resistor and a MiM capacitor positioned between metal levels 6 and 7 for low parasitic substrate coupling. One metal layer was added compared to the 130nm platform to facilitate the transition from thin wire to RF metallization.Figure 1 shows a TEM cross section of one of the first successful 90nm BiCMOS runs. Key challenges of the integration into the new CMOS node will be summarized in the presentation. The same device showed nearly ideal Gummel characteristics. CML ring oscillators with a design width EW of 190nm and 2.8 µm length achieved a wafer mean gate delay of 1.86ps with a standard deviation of 1.9%.Acknowledgment: This work was supported by the European Commission and the German Federal Ministry of Education and Research (BMBF) under project ref# 16ESE0202S ECSEL-TARANTO. [i] V. P. Trivedi et al., “A 90nm BiCMOS Technology featuring 400 GHz fMAX SiGe:C HBT”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2016, pp. 60-63. [ii] V. Jain et al., “Device and circuit performance of SiGe HBTs in 130nm BiCMOS process with fT/fmax of 250/330GHz,” IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 2014, pp. 96-99. [iii] P. Chevalier et al., “A 55 nm triple gate oxide 9 metal layers SiGe BiCMOS technology featuring 320 GHz fT / 370 GHz fMAX HBT and high-Q millimeter-wave passives,” in International Electron Devices Meeting (IEDM), 2014, pp. 3.9.1-3.9.3. [iv] J. Pekarik et al., “A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications,” in IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2014, pp. 92–95. [v] P. Hurwitz, R. Kanawati, K. Moen, E. Preisler, S. Chaudhry and M. Racanelli, "Advances in RF foundry technology for wireless and wireline communications," 2016 IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Austin, TX, 2016, pp. 5-8. [vi] J. Böck et al., “SiGe HBT and BiCMOS process integration optimization within the DOTSEVEN project”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2015, pp. 121-124. [vii] Q. Z. Liu et al, “SiGe HBTs in 90nm BiCMOS Technology demonstrating fT / fmax 285GHz / 475GHz through simultaneous reduction of base resistance and extrinsic collector capacitance”, ECS transactions, 64(6) , 2014, pp. 285 – 294. [viii] A. Fox, B. Heinemann, R. Barth, S. Marschmeyer, C. Wipf and Y. Yamamoto, "SiGe:C HBT architecture with epitaxial external base," 2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Atlanta, GA, 2011, pp. 70-73. [ix] V.T. Vu, D. Celi, T. Zimmer, S. Fregonese, P. Chevalier, “Advanced Si/SiGe HBT architecture for 28-nm FD-SOI BiCMOS”, in Bipolar / BiCMOS Circuits and Technology Meeting, 2016, pp. 64-67. [x] B. Heinemann et al., "SiGe HBT with fx/fmax of 505 GHz/720 GHz," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 3.1.1-3.1.4. [xi] D. Manger et al., "Integration of SiGe HBT with fT=305 GHz, fmax=537GHz in 130nm and 90nm CMOS," 2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), San Diego, CA, 2018, pp. 76-79. Figure 1

Analog circuit topology synthesis by means of evolutionary computation

Designing an analog electrical circuit requires substantial effort and time by a highly-skilled designer. Many tools have been devised to aid engineers in the design procedure, from simulators to parameter optimization tools, which largely assist in fine-tuning the parameter values of circuits with predetermined topologies. In this paper, we propose a new approach to circuit optimization that is capable of searching not only for the parameter but also the topological space. Starting from a high-level statement describing a desired circuit functionality, the proposed method can either improve a given circuit, or create a novel topology with given resources, based on the Darwinian theory of evolutionary selection. Our method uses a global parameter optimization method PSADE to speed up evolutionary convergence. We use the proposed algorithm (both single- and multi-objective) to successfully evolve passive, active, and BiCMOS circuits.

Introduction to the Special Section on the 2017 IEEE BCTM and IEEE CSICS Conferences

This Special Section of the IEEE Journal of Solid-State Circuits Features expanded versions of key invited papers that were presented at the 2017 IEEE Bipolar and BiCMOS Circuits and Technology Meeting (BCTM), held at Miami Marriott Biscayne Bay, Miami, FL, USA, on October 19–21, 2017, and the 2017 IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS), held also at Miami Marriott Biscayne Bay, Miami, FL, USA, on October 22–25, 2017.

Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS

This Special Section of the IEEE Journal of Solid-State Circuits presents the most interesting papers on integrated circuits from the 2016 IEEE Bipolar and BiCMOS Circuits and Technology Meeting (BCTM) and the 2016 IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS) which cover the latest research on silicon-germanium and III-V integrated circuits and their use in state-of-the-art communication, radar, and imaging systems.

Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.

Light-emitting device with monolithic integration on bulk silicon in standard complementary metal oxide semiconductor technology

A silicon light-emitting device is designed and realized in standard 3-μm complementary metal oxide semiconductor (CMOS) integrated circuitry. Accordingly, it can be integrated with its signal processing CMOS and BiCMOS circuits on the same chip, thus enabling the fabrication of much needed all-silicon monolithic optoelectronic systems operated by a single supply. The device emitted light in a broad, bell-shaped spectrum from 500 to 850 nm with characteristic peaks at 650 and 750 nm. Initial investigations indicate that the quantum efficiency is of the order of 10 −8 and the electric-to-optical power conversion efficiency is of the order of 10 −9 . This silicon light-emitting device has obvious applications in the electro-optical interconnect.

BiCMOS Flip-Flop Design Based on NPN-NPN Feedback Driver Circuits

based on the analyzing the characteristic of BiCMOS circuits and theory of transmission voltage-switches, we proposed a general structure of binary BiCMOS circuit based on NPN-NPN feedback driver circuit. Then we designed binary BiCMOS master-slave JK flip-flop circuit and transmission gate D flip-flop circuit base on the general structure of NPN-NPN feedback driver circuit. With using HSPICE simulation, the results show that the circuits have the correct logical function. The proposed driver circuits can be used in the design of BiCMOS sequential circuits.

On the Performance and Scaling of Symmetric Lateral Bipolar Transistors on SOI

The performance potential and scaling characteristics of thin-base SOI symmetric lateral bipolar transistors were examined using 1-D analytic equations for the currents and capacitances. The device can operate at collector current densities >100 mA/μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and it scales similarly to CMOS in terms of density. The physical base width is scalable to less than 20 nm. Multiple devices of different specifications can be integrated on a chip. A sample design is shown to have f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> > 200 GHz, f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> >1 THz, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> > 4V, and a self gain of 60. A balanced design is shown to have 350-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> and 700-GHz <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> , <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VA</i> of 2.4 V, and a self gain of 20. These results are superior to those reported for 32 nm SOI CMOS. The results suggest a need to rethink bipolar circuit design. They also suggest opportunities for novel bipolar and BiCMOS circuits. The devices in high-speed Si-base bipolar circuits operate at about 1.0 V. The path toward 0.5 V bipolar circuits is to use semiconductors with smaller bandgap, such as Ge.

Process-Induced Stress and Hydrogen Effects on Monolithic Integrated CMOS-MEMS Micro-Bimaterial Cantilever Sensor Array

Abstract A monolithic integrated bimaterial micro-cantilever resonant infrared sensor with on-chip auxiliary circuits was fabricated and tested. Surface micromachining method for cantilever fabrication has been merged with conventional CMOS process, and release of MEMS structure is conducted after CMOS process. Both the Cr/Au felling off the polysilicon cantilever during releasing process and the performance degradation of MOSFETs manufactured by standard CMOS or post-CMOS process are ascribed to the additive effects of hydrogen and mechanical stress. A novel post-CMOS process was raised to decrease the mechanical stress and to retain the metal layer of Cr/Au. On-chip digital/analog Bi-CMOS circuits function properly as demonstrated.

Electrical behavior research of silicon-on-insulator SiGe heterojunction bipolar transistor

The paper deals with the design optimization of SiGe heterojunction bipolar transistor (HBT) on thin film silicon-on-insulator (SOI). The basic DC and AC current characteristics are obtained and the differences between the SOI and bulk SiGe HBT are analyzed. As the incorporation of SOI substrate makes the SOI SiGe HBT a four-terminal device, the influences of the substrate bias on Gummel plot, output current and avalanche current are studied emphatically. Finally, the physical parameters of material and geometric parameters of the device are discussed by changing the frequency characteristics. Compared with the bulk counterpart, the SOI SiGe HBT is designed and fabricated with a great degree of freedom for better performance. This systematic analysis of SOI SiGe HBT provides a valuable reference for the SOI SiGe BiCMOS circuit design and simulation.

A collector space charge region model for SiGe HBT on thin-film SOI

SiGe heterojunction bipolar transistor (HBT) on thin film SOI has been successfully integrated with SOI CMOS by "folded collector". This paper deals with the collector of "partially depleted transistor" according to the thin film vertical SiGe HBT structure. A simplified circuit model including vertical and horizontal resistors and depletion capacitance is presented for the first time, and the model of the collector for field, voltage, and depletion width is systematically established. The model is analyzed with reasonable parameters. The results indicate that the space charge region consists of intrinsic junction depletion and MOS capacitance depletion, that the width of the space charge region increases with doping concentration of the collector, larger reverse junction voltage, and smaller substrate voltage, and that the region features a vertical expansion followed by a lateral expansion. This space charge region model of collector provides a valuable reference to the SiGe mm-wave BiCMOS circuit design and simulation on thin film SOI.

Functionalized Back-End Devices for (Bi)CMOS Circuits

The integration of various functionality to (Bi)CMOS circuits is in the focus of the "More than Moore" approach. Here, we demonstrate the incorporation of surface acoustic wave (SAW) devices as well as of nonvolatile memories (NVM) into the Back end of line (BEOL) of Bi(CMOS) circuits. The added functionalities open new technological possibilities for high value microelectronics systems.

Functionalized Back-End Devices for (Bi)CMOS Circuits

not Available.

A Fully Integrated Multisite Pressure Sensor for Wireless Arterial Flow Characterization

This paper presents a fully integrated battery-free sensing system that uses a two-site wireless pressure measurement for the detection of arterial stenosis. The remotely powered system uses a backscatter-modulated passive-telemetry interface and transmits sensor as well as reference information to an external system. The monolithic process used to realize the system integrates a 3 /spl mu/m BiCMOS circuit with silicon-on-glass absolute pressure sensors and an on-chip antenna. The wireless sensor interface consumes 340 /spl mu/W and uses capacitance-to-frequency conversion for readout of the vacuum-sealed pressure transducers. The integrated device has a 200 /spl mu/m profile and a volume of 2 mm/sup 3/. The system can sense a reduction in flow of 13%, corresponding to a differential pressure of 3 mmHg.

Horizontal Current Bipolar Transistor (HCBT) Process Variations for Future RF BiCMOS Applications

Two different process designs of horizontal current bipolar transistor (HCBT) technology suitable for future RF BiCMOS circuits are presented. The active transistor region is built in the defect-free sidewall of 900-nm-wide n-hills on a [110] wafer. The collector n-hill region is partially etched at the extrinsic base-collector periphery, whereas the extrinsic base is self-protected, resulting in reduced collector-base capacitance (C/sub BC/) and minimized volume of the extrinsic regions. The effect of doping levels at different regions on the transistor performance is examined in the two process designs. The fabricated HCBTs exhibit cutoff frequencies (f/sub T/) from 19.2 to 25.6 GHz, maximum frequencies of oscillations (f/sub max/) from 32.2 to 39.6 GHz, and collector-emitter breakdown voltages (BV/sub CEO/) between 4 and 5.2 V, which are the highest f/sub T/ and the highest f/sub T//spl middot/BV/sub CEO/ product compared to existing silicon-on-insulator (SOI) lateral bipolar transistors (LBTs). The compact nature of the HCBT structure and low-cost technology make it suitable for integration with advanced pillar-like CMOS and SOI CMOS devices.

Low-operating-voltage integrated silicon light-emitting devices

A solution is presented for the fabrication of low-voltage, low-power (<4.25 V and <5 mW) silicon light-emitting devices (Si-LEDs), utilizing standard very large scale integration technology without any adaptation. Accordingly, they can be integrated with their signal processing CMOS and BiCMOS circuits on the same chip. This enables the fabrication of much needed all-silicon monolithic optoelectronic systems operated by a single supply. The structural details of two distinctly different line-patterned Si-LEDs are presented, composed of heavily doped n/sup +/p/sup +/ junctions, made by BiCMOS n/sup +/ sinker and PMOS p/sup +/ source/drain doped regions, respectively. Using this approach, other Si-LED structures can be designed to yield low- or high-voltage Si-LED operation as well. Light is emitted at low reverse bias as a result of quantum transitions of carriers, generated by field emission, as indicated by the low reverse breakdown voltage V/sub B/, the soft knee I-V characteristics and the negative temperature coefficient of V/sub B/. The optical performance data show that, at low reverse operating current I/sub R/, the overall emitted light intensity L is a nonlinear function of I/sub R/ and becomes linear at higher I/sub R/. A bell-shaped light spectrum is obtained, with an enhanced short wavelength and attenuated long-wavelength radiation, relative to that of avalanche Si-LEDs.

Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits

The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFET parameters (L, Vth) to design BiCMOS digital circuits. The fTL relation is used in conjunction with the established BiCMOS gate delay models. It is shown that the minimum delay BiCMOS circuits driving the large capacitive load, can be designed at the transit frequency limit with the reduced BJT AREA factor. The time delay calculations are presented for a typical BiCMOS circuit and comparison is made with the results simulated using SPICE.

Low-power CMOS and BiCMOS circuits for analog convolutional decoders

Analog techniques have been proposed as a method of realizing high-speed low-power Viterbi decoders, mostly for use in digital magnetic recording applications. However, such methods can also be used in more general applications of the Viterbi algorithm, such as convolutional decoding. We describe two current-mode analog circuits for use in such applications. These circuits operate in excess of 100 MHz, and consume less than 4 mW per state, with 2.8-V supply rails when realized in 0.8-/spl mu/m technology.

BiCMOS implementation of a fuzzy system

BiCMOS circuits which can realise the different mathematical operations within a fuzzy system are presented in this paper. To maximise the operating speed of these circuits and increase the packing density, an analog approach is adopted throughout. The initial focus is on the design of circuits to implement fuzzification and intersection. The remainder of the paper focuses on the hardware implementation of implication and defuzzification, thus completing the fuzzy cell library. A major objective of this work is to maintain a design strategy which yields simple circuits so as to minimise cell density. Therefore, the circuits presented are relatively simple but effective with regard to the mathematical functions that they are required to generate within the cell. For example, fuzzification is achieved using the current spike derived from a CMOS inverter during switching. Both intersection and implication are realised using a single MOS transistor operating in the triode region. The remaining circuitry consists mainly of an operational amplifier in the summing mode to realise the function of defuzzification. The complete fuzzy system is simulated and a transfer characteristic is presented and discussed.