BiCMOS Circuits Research Articles

Trends in megabit DRAM circuit design

The state of the art in megabit dynamic random access memory (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio, power dissipation, and speed. The memory cell signal charge has decreased gradually with an increase in memory cell size, despite the vertically structured cell designs. To offset this decrease, multidivided data-line structures, low-power design, and transposition of folded data lines are essential. To reduce power dissipation, an increase in the maximum refresh cycle and multidivided data lines combined with shared I/O in addition to a reduced operating voltage are efficient. A BiCMOS circuit provides a high-speed access time with low cost due to the high drivability of the driver and high sensitivity of the amplifier. It is predicted that the current DRAM technology might be diversified in the future so that a large-memory-capacity-oriented technology would coexist with a high-speed-oriented technology, posing power-supply standardization as a continuing serious concern.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pull-down transient-imposed extrinsic base consideration in BiNMOS transistors

A detailed two-dimensional numerical simulation study of the bipolar devices in the BiCMOS circuit environment during pull-down transients is presented. The charge buildup and removal phenomenon in the bipolar device determines the switching speed of the BiNMOS devices. The tradeoffs in designing the extrinsic base in terms of the switching behavior are also described. It is shown that the structure with the extrinsic base p/sup +/ area farthest from the intrinsic base area has the best switching speed owing to the largest initial overshoot in the base voltage and the lateral base effects. >

Scaling of digital BiCMOS circuits

A generalized first-order scaling theory for BiCMOS digital circuit structures is presented. The effect of horizontal, vertical, and voltage scaling on the speed performance of various BiCMOS circuits is presented. The generalized scaling theory is used for the MOSFET, and the constant collector current (CIC) scaling scheme is used for the bipolar junction transistor (BJT). In scaling the bipolar transistor, polysilicon emitter contact and bandgap narrowing are taken into account. A case study for scaling BiCMOS circuits operating at 5- and 3.3-V power supplies shows that scaling improved BiCMOS buffers more significantly than CMOS buffers. Moreover, the low delay-to-load sensitivity of BiCMOS is preserved with scaling. >

Process integration and device performance of a submicrometer BiCMOS with 16-GHz f/sub t/ double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n/sup +/ buried layer, and n-channel MOSFETs were built in a p-well on a p/sup +/ buried layer. Deep trenches with depths of 4 mu m and widths of 1 mu m isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C/sub L/=0 pF and 300 ps for C/sub L/=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 mu m were maintained at almost the same ratio. >

Circuit modeling of bipolar transistors for BiCMOS

Modeling of a worst-type bipolar transistor implemented in a BiCMOS process is examined, and an appropriate DC model is developed for circuit simulation. This model is implemented as a SPICE subcircuit with various components representing parasitics associated with the transistor. The model can be adjusted by the removal of relevant parasitics to suit other BiCMOS implementations. The worst-type transistor considered has no buried layer or epitaxy, with the CMOS well forming the collector region. This results in a large and possibly nonlinear collector resistance. A high-gain parasitic substrate transistor is also present which leads to substrate current flow during transistor saturation. Collector resistance and substrate current are analyzed, and suitable expressions for these are included in the model without modification of SPICE models. Results are presented for n-p-n transistors in an n-well CMOS process and for p-n-p transistors in a p-well process. The model is used to simulate a simple analog BiCMOS circuit, and good agreement with measured results is obtained for circuit and parasitic currents. >