Bilayer Gate Stack Research Articles

High-temperature operation of Al2O3/Ga2O3 bi-layer gate stack GaN MOS-HEMT up to 450 °C with suppressed gate leakage

Abstract In this work, we report the reduced gate leakage current by using aluminum oxide (Al2O3) and gallium oxide (Ga2O3) as a bi-layer gate stack for GaN MOS-HEMT on a silicon substrate up to 450 °C. The bi-layer gate stack MOS-HEMTs suppressed the gate leakage by more than four orders of magnitude compared to only Al2O3-based GaN MOS-HEMT at 450 °C. The low gate leakage current is attributed to the reduced oxygen vacancies present in the Ga2O3 layer, which effectively impede the conduction path of the Poole-Frenkel emission at high temperatures, thereby enhancing the overall performance of GaN HEMTs.

Ferroelectric ZrO2 ultrathin films on silicon for metal-ferroelectric-semiconductor capacitors and transistors

Enhanced ferroelectric properties of nanoscale ZrO2 thin films by an HfO2 seed layer are demonstrated in metal-ferroelectric-semiconductor (Si) capacitors and transistors prepared with a low thermal budget of 400 °C. The seeding effect of the HfO2 layer leads to the enhancement of crystallization into the orthorhombic phase and the increase of remnant polarization of the sub-10 nm ZrO2/HfO2 bilayer structure. The ferroelectric field-effect transistor with the ZrO2/HfO2 bilayer gate stack reveals a large memory window of ~1.2 V and a steep subthreshold swing below 60 mV/decade. As compared with the Hf0.5Zr0.5O2 thin film, superior ferroelectric properties of the ZrO2/HfO2 bilayer structure show great potential for ferroelectric memory devices fabricated on Si substrates.

Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in transistor threshold voltage (Vth). The extent to which Vth drifts under certain stress conditions depends on (i) the defect ground-state energy distributions in the oxide bandgap, and (ii) the specific activation energy distributions for charge capture/emission process. In this work, semi-empirical modelling of ground-state defect energy distributions is revisited to determine the Total Operating Voltage Range of InGaAs-based MOSFETs for a DC-BTI lifetime of 10 years under DC operating conditions. Non-radiative Multiphonon (NMP) theory is subsequently used to describe the microscopic physics of charge (de-)trapping kinetics in terms of activation energy barriers for charge capture (EAc) and emission (EAe) into/from gate-stack defects. These activation energy barriers are visualized using Capture/Emission Time (CET) maps, which are efficient and powerful tools to predict the BTI degradation under different AC operating conditions as well. We demonstrate that the enhanced BTI reliability of a gate-stack with a novel ASM interfacial layer (ASM-IL), as compared to the bilayer gate-stack of Al2O3/HfO2, results from the favorable reconfiguration of the defect energy distribution in the oxide bandgap, as well as their activation energies for capture and emission process.

A comprehensive technique for estimation of process-induced fixed charges and effective work function of the metal gate on high- stack

An efficient generalized methodology is proposed for precise estimation of process-induced various fixed charge distributions in the dielectric layer and extraction of the effective work function (EWF) of the metal gate on double layer high-κ/SiO2 stack in metal-oxide-semiconductor (MOS) capacitors. Present technique is equally applicable for devices grown on multiple wafers with varying as well as uniform doping concentrations. The analysis is verified with experimentally obtained high-frequency capacitance–voltage (C–V) results by varying only the physical thickness of the high-κ dielectric layer on an interfacial silicon dioxide (SiO2) film of a fixed thickness in MOS devices fabricated using a wide variety of high-κ metal gate (HKMG) technologies including the recent advanced 28 nm high performance logic technology node. Presence of significant amount of positive bulk charges in the high-κ layer, negative fixed charges at the high-κ/SiO2 interface in addition to fixed oxide charges and interface traps at the Si/SiO2 interface are observed from our analysis. Furthermore, we have observed a negligible amount of bulk positive charges compared to the effective positive charges at the Si/SiO2 interface in TaN/SiO2/ capacitors. The present analysis applied on bi-layer gate stacks with different high-κ materials viz hafnium oxide (HfO2) and aluminum oxide (Al2O3) and also on single layer SiO2 dielectric processed under various conditions, reveals that RTA in N2 results nitrogen related negative oxide charges at the Si/SiO2 interface. However, annealing in N2 has no significant effect on reduction of number of interface traps at the Si/SiO2 interface.

Atomic-layer-deposited HfO2/Al2O3 laminated dielectrics for bendable Si nanomembrane based MOS capacitors

Flexible metal-oxide-semiconductor capacitors in a vertical structure using the single-crystalline Si nanomembrane (NM) with a HfO2/Al2O3 bilayer gate stack prepared by atomic layer deposition have been fabricated on plastic substrates by flip-transfer printing of Si NM/Ti/Au based trilayer heterostructures (1.3 cm × 0.9 cm × 360 nm). The electrical properties of the bilayer structure exhibit an excellent improved capacitance-voltage (C-V) frequency dispersion feature associated with an inhibited weak inversion hump and significantly larger accumulation capacitance, thus indicating the effectiveness of the passivation utilizing bilayer high-k dielectrics on a Si NM channel compared with monolayer HfO2. A comprehensive electromechanical characterization has been conducted for HfO2/Al2O3 stacked structures to investigate the effect of bending strain on C-V characteristics, leakage current density, and the associated evolution of interface charges. The presented research will be beneficial to realizing high performance thin-film transistors with lower operating voltage and higher driving current required in emerging flexible and stretchable electronics via optimized design of a nanolaminate gate stack and understanding the impact of mechanical strains on the electrical behavior of such MOS devices.

Low interface trap density in scaled bilayer gate oxides on 2D materials via nanofog low temperature atomic layer deposition

Al2O3 and Al2O3/HfO2 bilayer gate stacks were directly deposited on the surface of 2D materials via low temperature ALD/CVD of Al2O3 and high temperature ALD of HfO2 without any surface functionalization. The process is self-nucleating even on inert surfaces because a chemical vapor deposition (CVD) component was intentionally produced in the Al2O3 deposition by controlling the purge time between TMA and H2O precursor pulses at 50 °C. The CVD growth component induces formation of sub-1 nm AlOx particles (nanofog) on the surface, providing uniform nucleation centers. The ALD process is consistent with the generation of sub-1 nm gas phase particles which stick to all surfaces and is thus denoted as nanofog ALD. To prove the ALD/CVD Al2O3 nucleation layer has the conformality of a self-limiting process, the nanofog was deposited on a high aspect ratio Si3N4/SiO2/Si pattern surface; conformality of >90% was observed for a sub 2 nm film consistent with a self-limiting process. MoS2 and HOPG (highly oriented pyrolytic graphite) metal oxide semiconductor capacitors (MOSCAPs) were fabricated with single layer Al2O3 ALD at 50 °C and with the bilayer Al2O3/HfO2 stacks having Cmax of ∼1.1 µF/cm2 and 2.2 µF/cm2 respectively. In addition, Pd/Ti/TiN gates were used to increase Cmax by scavenging oxygen from the oxide layer which demonstrated Cmax of ∼2.7 µF/cm2. This is the highest reported Cmax and Cmax/Leakage of any top gated 2D semiconductor MOSCAP or MOSFET. The gate oxide prepared on a MoS2 substrate results in more than an 80% reduction in Dit compared to a Si0.7Ge0.3(0 0 1) substrate. This is attributed to a Van der Waals interaction between the oxide layer and MoS2 surface instead of a covalent bonding allowing gate oxide deposition without the generation of dangling bonds.

Nanoscale Characterization of High-K/IL Gate Stack TDDB Distributions After High-Field Prestress Pulses

The effect of single nondestructive pulsed voltage prestresses on the time to breakdown distributions of a SiON/HfSiON bilayer gate stack is investigated at nanometric scale using an atomic force microscope in conduction mode under ultrahigh vacuum. The results are compared with the degradation due to a voltage pulse of the SiON layer alone. It is found that only the shape parameters of the distributions are affected by the prestress pulses. This effect is then discussed in terms of a progressive degradation starting at the Si/SiON interface, and an extrapolation formula is given to predict the decrease of the time to breakdown of the bilayer gate stack as a function of the prestress pulse parameters.

Lg = 100 nm In0.7Ga0.3As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In0.53Ga0.47As MOS capacitors with BeO and Al2O3 and compared their electrical characteristics. As interface passivation layer, BeO/HfO2 bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In0.7Ga0.3As QW MOSFETs with a BeO/HfO2 dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (gm,max) of 1.1 mS/μm, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7 nm technology node and/or beyond.

Impact of bilayer character on High K gate stack dielectrics breakdown obtained by conductive atomic force microscopy

The time to breakdown distribution of bilayer gate stack dielectrics is measured at nanometric scale using an atomic force microscope in conduction mode under ultra-high vacuum. The bilayer consists of a SiON interfacial layer and a HfSiON High-K layer. Thanks to the small tip/sample contact area the time to breakdown distribution of the single interfacial layer is measured separately. It is found that the Weibull parameters of the Interfacial layer distribution are the same as those of the high percentile part of the bilayer bimodal distribution. This experimentally confirms the validity of former dielectric breakdown model assumptions. Considering the fields in each layer an accurate evaluation of acceleration factors and voltage scaling of the bimodal distribution are given.

HfO2/Al2O3 Bilayered High-k Dielectric for Passivation and Gate Insulator in 4H-SiC Devices

The electrical and chemical properties of high-k dielectric stacks consisting of Hafnium oxide (HfO2) and Aluminum oxide (Al2O3) deposited on 4H-SiC have been investigated by preparing metal insulator semiconductor (MIS) structures of HfO2/Al2O3/SiC. The bilayer gate stack was deposited by using atomic layer deposition (ALD). The samples were also treated by rapid thermal annealing (RTA) at 970°C for 5 mins in an inert gas atmosphere. Structural properties of the deposited films were analyzed with X-ray diffraction (XRD), atomic force microscopy (AFM) and Rutherford backscattering spectroscopy (RBS). Capacitance-voltage (CV) measurements performed on as-deposited and RTA treated structures at room temperature show that the RTA treatment increases the effective oxide charges in the whole dielectric but decreases the interface trap density. Current-voltage (IV) measurements have been performed in order to extract the leakage current density as well as the breakdown characteristics of the stack. Our results show that a combination of HfO2 and Al2O3 can be a better choice for SiC than individual Al2O3 layer because of the higher value of effective dielectric constant. It is shown that the stacked dielectrics are stable at high temperatures and under annealing conditions up to 300°C, which makes the layers compatible with SiC device processing and higher operating temperatures compared to silicon.

New Leakage Mechanism and Dielectric Breakdown Layer Detection in Metal-Nanocrystal-Embedded Dual-Layer Memory Gate Stack

We study the dielectric breakdown (BD) behaviors in MOS capacitor structures with metal-nanocrystal (NC)-embedded dual-layer (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) gate stack. Using a unique stressing methodology of inducing a BD path in one of the two dielectric layers, the effect of BD in the blocking or tunnel oxide is assessed. The first layer to BD is determined based on the physics underlying the Coulomb charging energy in relation to thermal energy gained by electrons at low voltage and in the very low temperature regime ranging from 11 K to 300 K. The established methodology to detect the BD layer in an NC-embedded dual-layer dielectric can be applied for any bilayered NC system, regardless of the thickness of the tunnel and blocking oxide layer. It is noted that BD in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> leads to lateral charging/discharging among NCs, while, in Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , it leads to spontaneous BD of bilayer gate stacks owing to high localized trap generation rate around the high-κ dielectric grain boundary and local electric field enhancement in the vicinity of metal NCs.

Atomic Layer Deposition of High-κ Dielectrics on Sulphur-Passivated Germanium

High mobility channels are currently being explored to replace the silicon channel in future CMOS technology nodes. However, until now the promising bulk properties are very difficult to translate into high transconductance due to a poor passivation of the interface between the gate dielectric and the channel. We have studied the S-passivation of the germanium surface combined with various high-permittivity dielectric gate stacks. (NH4)2S is used to achieve a S-terminated Ge surface. We found that the Ge/S/Al2O3 interface is superior to both the Ge/S/ZrO2 and Ge/S/HfO2 interfaces. Bi-layer stacks consisting of Ge/S/Al2O3/HfO2 or Ge/S/Al2O3/ZrO2 were built to achieve a gate stack with low EOT (Equivalent Oxide Thickness). In these bi-layer stacks, the Al2O3 thickness is reduced to a minimum without degradation of the interface properties. Rather thick Al2O3 interlayers (∼ 2 nm) are needed due to island growth on S-terminated Ge surface. A pMOSFET was built using a bi-layer gate stack (Ge/S/Al2O3/HfO2). The peak mobility of this device is > 200 cm2/Vs at an EOT of 1.5 nm.

ZrO2-Based InP MOSFETs (EOT ≈ 1.2nm) Using Various Interfacial Dielectric Layers

This paper presents the device performance of InP MOSFETs with a single ZrO2 gate dielectric and with stacked gate dielectrics using various interfacial layers between ZrO2 and InP substrate, including Al2O3, HfAlOx, and ZrAlOx. Of the gate stacks studied, Al2O3/ZrO2, HfAlOx/ZrO2, and ZrAlOx/ZrO2 bilayer gate dielectrics exhibit lower subthreshold swing, higher drive current and channel mobility compared to a single ZrO2 under similar equivalent oxide thickness of 1.2nm. In the reliability, InP MOSFETs with the bilayer gate stacks are more robust compared to that with a single ZrO2 under similar electrical field stress for 500s. These improvements are attributed to a better interface quality between the bilayer gate stacks and InP substrate, which has been confirmed by frequency dispersion and interface state density measurements.

TiO2/HfO2 Bi-Layer Gate Stacks Grown by Atomic Layer Deposition for Germanium-Based Metal-Oxide-Semiconductor Devices Using GeOxNy Passivation Layer

TiO2/HfO2 Bi-Layer Gate Stacks Grown by Atomic Layer Deposition for Germanium-Based Metal-Oxide-Semiconductor Devices Using GeOxNy Passivation Layer

Very high-κ ZrO2 with La2O3 (LaGeOx) passivating interfacial layers on germanium substrates

Thin La2O3 (LaGeOx) passivating layers combined with ZrO2 caps form a chemically stable bilayer gate stack on Ge with good electrical properties. The most important observation is that a higher-κ tetragonal zirconia phase coexists with the most commonly observed monoclinic, increasing the κ value of the oxide to about 32, thus benefiting the measured stack equivalent oxide thickness. This indicates that the ZrO2/La2O3 combination could be a promising candidate gate stack for Ge metal-oxide-semiconductor devices in terms of scalability.

Electrical and physical characterization of remote plasma oxidized HfO/sub 2/ gate dielectrics

Bi-layer gate stacks consisting of a HfO/sub 2/ and an interfacial layer are fabricated by remote plasma oxidation (RPO) of Hf metal deposited on an Si substrate. Hf metal is fully oxidized by the RPO even at a temperature as low as 400/spl deg/C due to radical oxygens, leading to an improvement in the quality of HfO/sub 2/ with less impact to the interfacial layer growth. An insufficient oxidation leads to a deterioration of mobility with increasing interface traps and positive bias temperature instability, which is likely caused by the oxygen vacancies acting as traps induced by the remaining Hf metal. The SiO/sub 2/-like interface improves the mobility with reduced interface states. Full oxidation and the controlled SiO/sub 2/-like interface demonstrate RPO as a promising way for gate-stack optimization.

Polysilicon-germanium gate patterning studies in a high density plasma helicon source

High density plasma etching processes using halogen based chemistries have been studied for 0.2 μm polysilicon-germanium gate patterning. Bilayer gate stacks consisting of 80 nm polycrystalline Si on 120 nm polycrystalline Si1−xGex (x was varied between 0.55 and 1) were grown on 4.5 nm SiO2 covered 200 mm diameter p-type silicon wafers. The bilayer gates were masked with oxide patterns. The wafers were etched in a low pressure, high density plasma helicon source. Various mixtures, based on Cl2, HBr, and O2 gases, have been used to investigate the etching of the Si/SiGe bilayer gates. The gas mixture and the plasma operating conditions have been optimized to obtain anisotropic etching profiles for features down to 0.2 μm, and to minimize the gate oxide consumption. Real time process control was achieved using HeNe ellipsometry in blanket areas, allowing the SiGe/oxide transition to be easily detected. A two step etching process using a Cl2/O2–He mixture was developed. The first step uses a high energy ion bombardment in order to obtain a high etch rate, and the second step uses a lower ion energy to achieve high SiGe/oxide selectivity. The second step is started 40 nm before reaching the SiGe/SiO2 interface in order to reduce gate oxide consumption and structural defects formation at the edges of the gate.