Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

Abstract

Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in transistor threshold voltage (Vth). The extent to which Vth drifts under certain stress conditions depends on (i) the defect ground-state energy distributions in the oxide bandgap, and (ii) the specific activation energy distributions for charge capture/emission process. In this work, semi-empirical modelling of ground-state defect energy distributions is revisited to determine the Total Operating Voltage Range of InGaAs-based MOSFETs for a DC-BTI lifetime of 10 years under DC operating conditions. Non-radiative Multiphonon (NMP) theory is subsequently used to describe the microscopic physics of charge (de-)trapping kinetics in terms of activation energy barriers for charge capture (EAc) and emission (EAe) into/from gate-stack defects. These activation energy barriers are visualized using Capture/Emission Time (CET) maps, which are efficient and powerful tools to predict the BTI degradation under different AC operating conditions as well. We demonstrate that the enhanced BTI reliability of a gate-stack with a novel ASM interfacial layer (ASM-IL), as compared to the bilayer gate-stack of Al2O3/HfO2, results from the favorable reconfiguration of the defect energy distribution in the oxide bandgap, as well as their activation energies for capture and emission process.