Basal Plane Dislocations Research Articles

Advances in defect characterization techniques using polarized light observation in SiC wafers for power devices

This short review provides an overview of advancements in the characterization of defects in silicon carbide (SiC) wafers using polarized light observation. SiC, which has a wide bandgap and excellent thermal and electrical properties, is widely used in power devices. However, various defects such as threading screw dislocations (TSD), threading edge dislocations (TED), and basal plane dislocations (BPD) can significantly affect device performance and reliability. Polarized light observation offers a nondestructive method for visualizing these defects and analyzing the stress fields induced within the SiC crystal structure. This paper summarizes recent developments in this technique, including the application of analyzer rotation to enhance the contrast in defect visualization. Furthermore, the development of automated systems for rapid wafer evaluation is discussed, highlighting the role of polarized light observation in improving quality control and production efficiency in SiC power device manufacturing.

Effect of the N-doping concentration on the formation of the wide carrot defect in 4H-SiC homoepitaxial layer grown by trichlorosilane (TCS) as silicon precursor

The effect of epilayer growth system, growth rate and N-doping concentration on the formation of the wide carrot defects in 4H-SiC homoepitaxial layer was investigated in this work. We found that the wide carrot defect formed on 4H-SiC epilayer only with low N-doping concentration of 5 × 1014 cm−3 grown by the SiHCl3+C2H4+H2 (TCS) system, which is different with the previous reports on the SiH4+C3H8+H2 growth system that can form such defect regardless of N-doping concentration. Besides, such wide carrot defect was never found on high speed growth of epilayer surface grown by TCS growth system. The morphology and structure of wide carrot defects were characterized by optical microscope (OM), micro-photoluminescence (PL) spectroscopy, atomic force microscope (AFM) and molten KOH etching. We speculate that the amount of wide carrot defects is related with the basal plane dislocations (BPDs) density which depends on the epitaxial growth system, growth rate of epilayer and the N-doping concentration. The formation mechanism and elimination methods of these wide carrot defects were proposed.

Investigation of Threshold Voltage Instability and Bipolar Degradation in 3.3 kV Conventional Body Diode and Embedded SBD SiC MOSFET

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

A Study of Process Interruptions during Pre- and Post-Buffer Layer Epitaxial Growth for Defect Reduction in 4H SiC

We perform epilayer growth where the process is interrupted (in situ) during post and pre buffer layer growth at a reduced temperature. Process interrupted during post buffer layer growth demonstrates significant reduction in basal plane dislocation (BPD) at a lower temperature. SIMS study demonstrates that etching takes place during the interruption time. We believe surface treatment of the buffer layer at different etching conditions during the interruption plays a major role in BPD reduction. However, the in-situ interruption, taking place prior to the buffer layer (i.e., on the substrate), does not contribute to the reduction in BPD in epilayer. We believe that the surface effect of interruption related etching on substrate during pre-buffer layer interruption, is not efficient enough to reduce BPD due to the higher doping and higher BPD associated with the substrate. Furthermore, we demonstrate that post buffer layer growth interruption contributes to the reduction in stacking faults in the epilayers. We also attribute this reduction of SF due to the surface etching prior to the drift layer growth.

The Role of Defects on SiC Device Performance and Ways to Mitigate them

Several defects were analyzed through the manufacturing chain along with their impact on devices. High kill rate of micropipes were seen on both Diodes and MOSFETs as expected. The purity of micropipe detection was found to be affected by the presence of inclusions. Inclusions were successfully sub-classified and separated out from micropipes, based on their location depth from the wafer surface. The effect on devices was found to relate to how deep the inclusion was located, with the ones at the surface having the biggest impact. Various sources of Stacking Faults (SFs) were reported, with Basal Plane Dislocations (BPDs) in the crystal being a major contributor. Higher local densities of BPDs were found to have a more detrimental effect. SFs were sub-classified using the wavelength of each peak. The effect of both overall SFs and each SF sub-type on devices was determined, each sub-type having different effect on the device. Various ways of mitigating the effects of defects and dislocations are demonstrated. Reducing killer defects, SF nucleation probability, and BPDs propagation by epitaxial process optimizations are shown. Resilience up to 3500A/cm2 against bipolar degradation is demonstrated by using an engineered buffer layer. Process and device design optimizations show high resiliency against crystal and epi defects and dislocations, with improved yield and lower leakage.

Investigation of BPD Faulting under Extreme Carrier Injection in Room vs High Temperature Implanted 3.3kV SiC MOSFETs

Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x1018 cm-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x1019 cm-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

Analysis of Forward Bias Degradation Reduction in 4H-SiC PiN Diodes on Bonded Substrates

Analysis of forward bias degradation reduction of 4H-Silicon Carbide (4H-SiC) PiN diodes on bonded substrates was performed. In the analysis, cathodoluminescence (CL), photoluminescence imaging (PL imaging), and transmission electron microscope (TEM) were used. Under high forward bias stress, the Shockley-type stacking fault (SSF) does not expand into the transferred layer of the bonded substrate, while in the monocrystalline substrate, the SSF expands below the epilayer/substrate interface. The basal plane dislocation (BPD) within the transferred layer does not expand to the SSF. The transferred layer has the effect of suppressing the expansion of SSFs. This effect can be caused by hydrogen implantation for wafer splitting to produce bonded SiC substrates.

Accuracy of EVC Method for the PiN Diode Pattern on SiC Epi-Wafer

In the previous report, we proposed the EVC (Expansion-Visualization-Contraction) method (Fig. 1) that effectively screens for malignant BPDs (basal plane dislocations) in the epi layer and near substrate interface, which expand to SSFs (Shockley-type stacking faults), leading to forward voltage degradation. The method intentionally utilizes the REDG (recombination enhanced dislocation glide) mechanism by UV (ultraviolet) irradiation in wafer sorting to replace the so-called burn-in (accelerated current stress) process, which is time-consuming during mass production. In this report, to verify the effectiveness of this method, we compared the SSFs expanded by forward biasing the PiN diode (Fig.3) on a wafer with the SSFs expanded by UV irradiating at the same PiN diode area where the metal electrode was removed by etching. The accuracy of the EVC method requires that SSFs expanded by forward biasing should be detected in the same positions as those of SSFs expanded by UV irradiation. Not all BPDs expand at the same time, but the number of expanded SSFs increases over time under constant forward current conditions. In this experiment, the current density was 400 A/cm2 for 8 minutes, and the excessive UV irradiation conditions was 143 W/cm2 for 20 minutes to avoid missing. Missing means the inability to check the SSFs expanded by forward biasing against the SSFs expanded by UV irradiation (Fig.2). For each diode electrode window, the presence or absence of SSFs were determined, and as shown in Table 2, 2 out of 49 window areas were missing, with the EVC method accuracy rate of 96 %.

High-Volume SiC Epitaxial Layer Manufacturing-Maintaining High Materials Quality of Lab Results in Production

Typically, research and development (R&D) results of epitaxial layer growth show superior properties of the grown layers compared to high volume results. Layer uniformities are excellent and achieved defect densities are low compared to typical results. In particular, the conversion of basal plane dislocations (BPD) from the silicon carbide (SiC) substrate is in focus to reduce bipolar degradation of p-n-junctions. It is a great challenge to maintain those excellent results in high-volume manufacturing considering all the factors that impact the properties of the epilayer. Thus, quality of the layers, high throughput and low cost have to be assessed to find a compromise between these key factors. In this paper we present results on the growth of epitaxial layers on 150 mm and 200 mm 4° off-oriented 4H-SiC substrates using warm-wall multi-wafer chemical vapor deposition (CVD) systems. Single wafer data of the key epitaxial layer parameters, thickness, doping and defect densities, are compared to batch and lot results, as well as to statistical data of several hundreds of wafers produced. Improvements in wafer-to-wafer (w-t-w) doping uniformity could be achieved for instance by implementation of an on-wafer temperature measurement. Substrate impact on defect levels is shown comparing X-ray topography (XRT) results of bare substrate wafers and defect analysis of epilayers on sister wafers from the same crystal. Statistical defect data and resulting predicted yield loss also show a dependence on substrate suppliers. For the first time we show w-t-w and run-to-run (r-t-r) results of doping and thickness measurements on 200 mm substrates. Also, defect results of epilayers on 200 mm wafers are compared to results on 150 mm.

Macro Step Bunching/Debunching Engineering on 4° off 4H-SiC (0001) to Control the BPD-TED Conversion Ratio by Dynamic AGE-Ing<sup>®</sup>

This paper presents an investigation into the surface morphology control of 4H-SiC (0001) wafers cut to 4º off during thermal processing, aiming to suppress the propagation of basal plane dislocations (BPD) into the epitaxial growth layer. Developing methods for debunching rough surfaces with macro step bunching (MSB) using thermal processes removes many of the limitations of the conventional epitaxial growth process. This study presents a surface morphology control method that includes debunching of steps by thermal sublimation etching/growth using the Dynamic AGE-ing® (DA) method. By controlling the surface morphology before and after growth using this method, the dependence of the BPD-threading edge dislocation (TED) conversion ratio on surface morphology was systematically revealed. By selecting the optimal pre- and post-growth surface morphology, a 100 % BPD-TED conversion ratio was obtained for the 10 mm × 25 mm area. It was indicated that an innovative and stable surface morphology control technique using the DA sublimation process could solve numerous technological challenges in various fields.

Investigation of Dislocation Behaviors in 4H-SiC Substrate during Post-Growth Thermal Treatment

Dislocation behaviors after post-growth thermal treatment were investigated by X-ray topography and KOH etching. Generation of prismatic dislocations were observed in X-ray topography, and density of basal plane dislocations (BPDs) increases with annealing temperature and radial temperature gradient. Distribution of newly generated BPDs in the wafer after thermal treatment is correlated to the resolved shear stress arising from radial temperature gradient.

Evaluation of Basal Plane Dislocation Behavior near Epilayer and Substrate Interface

An essential silicon carbide (SiC) manufacturing procedure for eliminating bipolar degradation in a SiC device is the detection of the basal plane dislocation (BPD) causing the phenomenon. In this work, we employed the mirror electron microscope (MEM) technique, which has higher resolution than photoluminescence. The MEM provided results for the detection of short BPDs without conversion to threading edge dislocation at the epi/sub interface. In addition, a considerable number of short BPDs were observed in the epilayer grown with the improved method, and the conversion ratio around the buffer layer could be derived.

Proposal of Damage-Free SiC Wafer Dicing Using Water Jet Guided Laser

A damage-free SiC wafer dicing method has been strongly required for practical applications of power devices. In this research, we propose water jet guided laser processing as a novel dicing method. Water jet guided laser processing, which uses a high-pressure fine water jet as waveguide, could generate no cracks or dislocations in crystal. In this paper, water jet guided laser grooving quality was evaluated to demonstrate there should be no chippings and basal plane dislocations. Scanning electron microscopic and X-ray topography observations were conducted. The results indicated the superiority of water jet guided laser dicing to a conventional dicing method.

Molecular Dynamics Study on the Mechanical Behaviors of Nanotwinned Titanium

Titanium and titanium alloys have been widely applied in the manufacture of aircraft engines and aircraft skins, the mechanical properties of which have a crucial influence on the safety and lifespan of aircrafts. Based on nanotwinned titanium models with different twin boundary spacings, the impacts of different loadings and twin boundary spacings on the plastic deformation of titanium were studied in this paper. It was found that due to the different contained twin boundaries, the different types of nanotwinned titanium possessed different dislocation nucleation abilities on the twin boundaries, different types of dislocation–twin interactions occurred, and significant differences were observed in the mechanical properties and plastic deformation mechanisms. For the {101-2} twin, basal plane dislocations were likely to nucleate on the twin boundary. The plastic deformation mechanism of the material under tensile loading was dominated by partial dislocation slip on the basal plane and face-centered cubic phase transitions, and the yield strength of the titanium increased with decreasing twin boundary spacing. However, under compression loading, the plastic deformation mechanism of the material was dominated by a combination of partial dislocation slip on the basal plane and twin boundary migration. For the {101-1} twin under tensile loading, the plastic deformation mechanism of the material was dominated by partial dislocation slip on the basal plane and crack nucleation and propagation, while under compression loading, the plastic deformation mechanism of the material was dominated by partial dislocation slip on the basal plane and twin boundary migration. For the {1124} twin, the interaction of its twin boundary and dislocation could produce secondary twins. Under tensile loading, the plastic deformation mechanism of the material was dominated by dislocation–twin and twin–twin interactions, while under compression loading, the plastic deformation mechanism of the material was dominated by partial dislocation slip on the basal plane, and the product of the dislocation–twin interactions was basal dislocation. All these results are of guiding value for the optimal design of microstructures in titanium, which should be helpful for achieving strong and tough metallic materials for aircraft manufacturing.

Characterization of extended defects in 2D materials using aperture-based dark-field STEM in SEM

Quantitative diffraction contrast analysis with defined diffraction vectors is a well-established method in TEM for studying defects in crystalline materials. A comparable transmission technique is however not available in the more widely used SEM platforms. In this work, we transfer the aperture-based dark-field imaging method from the TEM to the SEM, thus enabling quantitative diffraction contrast studies at lower voltages in SEM. This is achieved in STEM mode by inserting a custom-made aperture between the sample and the STEM detector and centering the hole on a desired reflection. To select individual reflections for dark-field imaging, we use our Low Energy Nanodiffraction (LEND) setup [Schweizer et al., Ultramicroscopy 213, 112956 (2020)], which captures transmission diffraction patterns from a fluorescent screen positioned below the sample. The aperture-based dark-field STEM method is particularly useful for studying extended defects in 2D materials, where (i) stronger diffraction at the lower voltages used in SEM is advantageous, but (ii) two-beam conditions cannot be established, making quantitative diffraction contrast analysis with standard bright-field and annular dark-field detectors impossible. We demonstrate the method by studying basal plane dislocations in bilayer graphene, which have attracted considerable research interest due to their exceptional structural and electronic properties. Direct comparison of results obtained on identical dislocations by the established TEM method and by the new aperture-based dark-field STEM method in SEM shows that a reliable Burgers vector analysis is possible by applying the well-known g·b=0 invisibility criterion. We further use the LEND setup to acquire 4D-STEM data and show that the virtual dark-field images match well with those in aperture-based dark-field STEM images for reliable Burgers vector analysis.

Discrimination of dislocation in highly doped n-type 4H–SiC by combining electrochemical reaction and molten alkali etching

This work proposes an effective etching method for highly doped n-type 4H–SiC by combining electrochemical reactions and molten alkali etching. By employing our developed method, threading mixed dislocation (TMDs) and threading screw dislocations (TSDs) can be distinctly visualized as hexagonal etching pits of varying sizes. The slightly smaller threading edge dislocations (TEDs) appear as roughly circular etching pits, while basal plane dislocations (BPDs) are revealed as characteristic seashell-shaped pits. Additionally, we provide a reaction equation that elucidates the mechanism of the electrochemical etching process, thus sparking a new investigation into the discrimination of dislocations under molten alkali conditions. By applying a positive voltage to the wafer, we ensure a continuous supply of holes crucial for the reaction, thereby maintaining both the etching rate and the selectivity towards defects. This approach not only enhances the efficiency of the etching process but also provides a more accurate and reliable method for characterizing and understanding the dislocation properties of highly doped n-type 4H–SiC wafers.

Suppression of stacking-fault expansion in 4H-SiC diodes by helium implantation

Abstract Bipolar degradation is a critical problem in Silicon carbide devices, caused by the expansion of single Shockley stacking faults (1SSFs) from basal plane dislocations. This paper presents the effects of helium implantation on the suppression of 1SSFs expansion. The fabricated PiN diodes were analyzed using current–voltage characteristics and electroluminescence imaging. The results show that helium implantation can effectively suppress 1SSFs expansion without significantly degrading diode performance. We consider that this suppression is due to the pinning of dislocations by point defects introduced during helium implantation, and the reduction of carrier lifetime may also play a role in suppressing 1SSFs expansion.

The effect of shear on nucleation and movement of basal plane dislocations in 4H-SiC

The effect of shear on nucleation and movement of basal plane dislocations in 4H-SiC

The Numerical Simulations and Experimental Study of an 8-Inch SiC Single Crystal with Reduced BPD Density.

The basal plane dislocation (BPD) density is one of the most important defects affecting the application of SiC wafers. In this study, numerical simulations and corresponding experiments were conducted to investigate the influence of cooling processes, seed-bonding methods, and graphite crucible materials on the BPD density in an 8-inch N-type 4H-SiC single crystal grown by the physical vapor transport (PVT) method. The results showed that the BPD density could be effectively reduced by increasing the cooling rate, optimizing the seed-bonding method, and adopting a graphite crucible with a similar coefficient of thermal expansion as the SiC single crystal. The BPD density in the experiments showed that a high cooling rate reduced the BPD density from 4689 cm-2 to 2925 cm-2; optimization of the seed-bonding method decreased the BPD density to 1560 cm-2. The BPD density was further reduced to 704 cm-2 through the adoption of a graphite crucible with a smaller thermal expansion coefficient.

Effects of terraces and steps on the 4H-SiC BPD-TED conversion rate: A reaction pathway analysis

The practical use of 4H-SiC as a semiconductor material alternative to Si has been investigated by several researchers. However, a key challenge impeding its practical implementation is the elimination of killer defects in the epitaxial layer, such as basal plane dislocations (BPDs), which cause bipolar degradations. The conversion of BPDs into threading edge dislocations is crucial to reduce detrimental mobile dislocations. However, their underlying atomistic mechanisms remain unclear. In this study, the effects of the step height and distance from the step on the contraction of BPDs were determined using a reaction pathway analysis. Notably, the step height did not affect the contraction, and the activation energies for the contraction of the partial dislocation pairs with Burgers vectors closed toward the step were 0.4 (C face) and 0.3 eV (Si face) lower than those for expansion. Conversely, for the partial dislocation pairs with Burgers vectors open toward the step, the activation energies for contraction were 0.4 (C face) and 0.2 eV (Si face) higher than those for expansion. Furthermore, the effect of the step diminished when the distance from the step exceeded 3 nm. The results suggest that the steps prevented contraction, and longer terraces reduced this preventive effect. Therefore, a surface morphology with fewer steps and longer terraces would increase the conversion rate. Furthermore, a low-off-angle substrate and surface polishing would increase the conversion rate, whereas step bunching slightly would decrease it. Macrosteps would decrease the conversion rate as the average distance from the surface to BPDs increased.