The Role of Defects on SiC Device Performance and Ways to Mitigate them

Abstract

Several defects were analyzed through the manufacturing chain along with their impact on devices. High kill rate of micropipes were seen on both Diodes and MOSFETs as expected. The purity of micropipe detection was found to be affected by the presence of inclusions. Inclusions were successfully sub-classified and separated out from micropipes, based on their location depth from the wafer surface. The effect on devices was found to relate to how deep the inclusion was located, with the ones at the surface having the biggest impact. Various sources of Stacking Faults (SFs) were reported, with Basal Plane Dislocations (BPDs) in the crystal being a major contributor. Higher local densities of BPDs were found to have a more detrimental effect. SFs were sub-classified using the wavelength of each peak. The effect of both overall SFs and each SF sub-type on devices was determined, each sub-type having different effect on the device. Various ways of mitigating the effects of defects and dislocations are demonstrated. Reducing killer defects, SF nucleation probability, and BPDs propagation by epitaxial process optimizations are shown. Resilience up to 3500A/cm2 against bipolar degradation is demonstrated by using an engineered buffer layer. Process and device design optimizations show high resiliency against crystal and epi defects and dislocations, with improved yield and lower leakage.