Bandgap Voltage Research Articles

A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations

This brief proposes a resistor-less bandgap reference (BGR) based on a leakage-based proportional-to-absolute-temperature (PTAT) scheme. The effect of process variations on the current is mitigated by employing self-biased current-limiting MOS transistors. The bias voltages needed for approximating a large resistance can be obtained from a single branch by placing threshold-sampling transistors on top of the BGR output. The fabricated BGR in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS occupies an active area of 0.035 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 20.5 nW, and it shows a standard deviation of 0.68% at untrimmed reference voltages.

Low-noise delta-sigma analog front end with capacitor swapping technique for capacitive microsensors

In this paper, low-noise incremental delta–sigma analog front end (AFE) integrated circuit (IC) for capacitive microsensors is presented. A conventional capacitance-to-digital converter (CDC) mainly uses a multi-stage capacitive sensing amplified stage (CSA) and analog-to-digital converters. The multi-stage CSA is not suitable for application in various Internet of things (IoT) devices that require low power because the power consumption of the analog front-end circuit increases in proportion to the number of amplifiers and the chip area increases. So, the presented delta-sigma AFE can convert the capacitance changes to the digital codes directly. This structure can achieve a small active area and low power consumption. The delta–sigma AFE achieves low-noise and high linearity using a capacitor polarity swapping technique. The measured effective resolution is 16.2 bits, and the non-linearity is 0.05% full-scale output (FSO). The integrated circuit is implemented in a 0.18-µm standard CMOS process. All functional blocks, including the analog circuits (bandgap reference, voltage reference, and delta–sigma capacitance-to-digital converter) and digital block (accumulator and timing generator), are integrated on a chip. The proposed incremental delta–sigma AFE consumes 1.12 mW of power from a 3.3-V supply at a sampling frequency of 500 kHz and occupies a total active area of 0.42 mm2.

ASET and TID Characterization of a Radiation Hardened Bandgap Voltage Reference in a 28-nm Bulk CMOS Technology

Analog single-event transient (ASET) and total ionizing dose (TID) characterization of a radiation-hardened bandgap voltage reference (BGR) is investigated in a 28-nm commercial bulk CMOS technology. Different radiation hardened by design (RHBD) techniques are used for ASET mitigation in the circuit and layout, and the circuit is optimized to ensure the BGR can still work correctly even using fast nMOS and slow pMOS for TID mitigation. Heavy-ion (linear energy transfer (LET) = 76.3 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg) experiments show the maximum amplitude of positive (negative) ASET is just 30 mV (90 mV), and Co <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> gamma-ray experiments show the maximum output voltage reduction is just 37 mV after 1.2 Mrad(Si) irradiation, and the final output voltage reduction is just 11 mV after 48 h of annealing. All of the experiments indicate that ASET is significantly mitigated by the RHBD techniques, and the BGR has naturally good TID response due to the design margin. The investigation also indicates that the proposed BGR is a good substitute for space application due to the excellent ASET and TID tolerance capability.

Improving the photovoltaic properties of GaAs/GaAsBi pin diodes by inserting a compositionally graded layer at the hetero-interface

We investigated the effect of inserting a compositionally graded layer at the GaAsBi/GaAs interface on the photovoltaic and light-emission properties of GaAs/GaAsBi pin diodes. When the pin diode is operated as a solar cell, inserting a graded layer improves the open-circuit bandgap–voltage offset (W oc) to 0.51 V. This is comparable to or better than other materials—such as GaInNAs(Sb), which has a bandgap of 1.0 eV—that are expected to be used in multijunction solar cells. In contrast, W oc can be as large as 0.71 V for a pin diode without a graded layer. When it is operated as a light-emitting diode, inserting a graded layer in such a diode suppresses nonradiative recombination by a factor of 1/50 based on its electroluminescence intensity. Inserting a graded layer also makes it possible to avoid deterioration of the peculiar hetero-interface where the transition from the non-metallic nature of GaAs to the metallic nature of GaAsBi occurs. Moreover, the graded layer is effective in avoiding a pile-up of oxygen at the interface at low temperatures when growth is interrupted just before growing the GaAsBi layer. Thus, inserting a graded layer is the key to improving the performance of minority-carrier devices containing GaAsBi.

A Low-temperature-coefficient Bandgap Voltage Reference for Sar Adc

Abstract The paper verifies a curvature-compensated bandgap reference circuit, which generates 1.2V bandgap voltage. Bandgap voltage comprises two parts: proportional to absolute temperature (PTAT) voltage from the bandgap core and complementary to absolute temperature (CTAT) voltage from the p-n junction. Simulation results across corners show that the temperature coefficient of this architecture can be less than 3ppm/°C by using the current compensation. Test results prove that the temperature coefficient achieves 5ppm/°C. The proposed bandgap consumes a power of 2mW and occupies an area of 0.15mm2 in the 0.18μm CMOS process.

A Simple Structure With Low Temperature Drift Bandgap Voltage Reference Design

Due to the dilemma between the temperature coefficient and the structural complexity of the traditional bandgap voltage reference, a simple bandgap voltage reference with low temperature coefficient is proposed in this paper. Based on the Brokaw bandgap circuit structure, making the structural innovation. The requirement of the traditional structure for high gain amplifier is abandoned and the current mirror structure is used to realize the current proportional relation, which simplifies the circuit structure. The negative feedback path makes the results more accurate. Intriguingly, under 3.3V power supply voltage, using TSMC 0.18μm CMOS process, SPECTRE simulation results show that, when the temperature of the output voltage of the bandgap voltage reference is -65°C~150°C, the temperature coefficient is 12.79ppm/°C, and the PSRR is 79.85dB, noise is 5.636 UV and start-up time is 200ns.

A 2.5 V, 2.56 ppm/°C Curvature-Compensated Bandgap Reference for High-Precision Monitoring Applications.

This work presents a high-precision high-order curvature-compensated bandgap voltage reference (BGR) for battery monitoring applications. The collector currents of bipolar junction transistor (BJT) pairs with different ratios and temperature characteristics can cause greater nonlinearities in ΔVEB. The proposed circuit additionally introduces high-order curvature compensation in the generation of ΔVEB, such that it presents high-order temperature effects complementary to VEB. Fabricated using a 0.18 µm BCD process, the proposed BGR generates a 2.5 V reference voltage with a minimum temperature coefficient of 2.65 ppm/°C in the range of −40 to 125 °C. The minimum line sensitivity is 0.023%/V when supply voltage varies from 4.5 to 5.5 V. The BGR circuit area is 382 × 270 μm2, and the BMIC area is 2.8 × 2.8 mm2.

An Accurate Bandgap Voltage Reference Ready-Indicator

An accurate indication that the bandgap voltage reference (BGR) circuit is settled on its nominal value is essential in analog or mixed signal systems. In this paper, a generic method for accurate bandgap voltage reference (BGR) Ready-Indication (RI) is proposed. A RI signal shows that the BGR operates correctly but also is used to enable PoR circuits when those employ the bandgap voltage to generate the required thresholds. In many low power applications, several systems are periodically switched on and off to save power and to increase battery life. In such systems, most circuits must remain off, while BGR is not in ready mode, saving battery energy. In other critical applications, the Ready-Indicator can ensure that critical systems can be set on and the reference voltage is within the operating range. In this paper, the introduced methodology is applied to different reference voltage generators. Initially, a BGR with Ready-Indication is presented extensively, including post-layout simulations results in 22 nm, while thereafter, the study of this method is extended in other BGR topologies. The universality of the proposed method is proved by verifying the operation in all the BGR topologies under study covering designs in 22 nm and 65 nm and with supply voltages 1.8 V, 1 V, 0.55 V.

Switched-Capacitor Bandgap Voltage Reference for IoT Applications

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {EB}}$ </tex-math></inline-formula> generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/&#x00B0;C at 0.5V supply within &#x2212;40 &#x00B0;C to 120 &#x00B0;C. The line regulation is 3.3mV/V or 0.66&#x0025;/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a <inline-formula> <tex-math notation="LaTeX">$3\sigma / \mu $ </tex-math></inline-formula> variation of 1.37&#x0025; before trimming, while 0.25&#x0025; after applying one-point trimming at 20&#x00B0;C.

A curvature-compensated bandgap voltage reference with a temperature coefficient trimming circuit

This paper presents an advanced topology of bandgap voltage reference (BGR) which consists of a novel curvature-compensated circuit and a current-mode trimming circuit. A positive-temperature-coefficient (positive-TC) nonlinear term is produced in the difference between the base-emitter voltages of two bipolar junction transistors (ΔVBE) to realize the high-order curvature compensation. The ΔVBE is generated by adding a negative-TC current into the bandgap core. Owing to the compensated ΔVBE, the BGR could be fine-tuned by an innovative current-mode trimming circuit which takes less area and achieves a larger trimming range. Benefiting from the trimming circuit, the PVT stabilities of proposed BGR are improved. Designed in a 0.18 μm HVCMOS process, the BGR occupies an active area of 267μm×226μm. The post-layout simulation results show the BGR reaches a low TC of 1.64 ppm/∘C in a wide range of -55 °C to 125 °C.

A Curvature Compensation Technique for Low-Voltage Bandgap Reference

Based on the standard 40 nm Complementary Metal Oxide Semiconductor (CMOS) process, a curvature compensation technique is proposed. Two low-voltage, low-power, high-precision bandgap voltage reference circuits are designed at a 1.2 V power supply. By adding IPTAT (positive temperature coefficient current) and ICTAT (negative temperature coefficient current) to the output resistance, the first-order compensation bandgap voltages can be obtained. Meanwhile, the third high-order compensation current is also superimposed on the same resistance. We make use of the collector current of the bipolar transistor to compensate for the nonlinear term of VBE. The simulation results show that TC (temperature coefficient) of the first circuit reference could be reduced from 29.1 × 10−6/°C to 5.71 × 10−6/°C over the temperature range of −25 to 125 °C after temperature compensation. The second one could be reduced from 17 × 10−6/°C to 5.22 × 10−6/°C.

Simulation study on the diversity and characteristics of twin structures in GaN

Gallium nitride (GaN) is a promising material for high-frequency and high-power electronics owing to its high thermal stability, wide bandgap, and high breakdown voltage. Monocrystalline GaN films are usually produced by metal organic chemical vapor phase deposition using Si, SiC, or Al 2 O 3 as the substrate. However, the difference in lattice constants and thermal expansion coefficients causes many defects in GaN epilayers . In particular, the formation of twins will strongly influence the electronic properties of GaN-based devices. In this study, the solidification process of GaN was simulated by molecular dynamics at a cooling rate of 10 12 K/s, and the twin structures in GaN were discussed. The results of this simulation showed two types of twins, including coherent twin and rotating twin, which were analyzed by visualization technology. The formation of twins was related to the coexistence of zinc blende and wurtzite phases. Furthermore, the types of twins were closely associated to the stacking ways of zinc blende and wurtzite structures. In general, it is essential to study the microstructure and the structural evolution of twin GaN, in order to give references to experiments about the growth and characteristics of twins. • Zinc blende and wurtzite nucleated randomly and formed lots of complex structures at the beginning of crystallization. • Coherent and rotating twins were formed according to different stacking methods of zinc blende and wurtzite structures. • The rules for the combination of twin structures in GaN crystals have been summarized and it can be generalized. • An error in the stacking sequence can cause the metastable phase c-GaN to start seeding the h-GaN phase.

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A2-Comparator and Sleep-Time Detector for IoT Application

An ultralow-quiescent current dc-dc buck converter with a single controller is presented to achieve high efficiency over a wide load range for Internet of Things application, which is achieved by utilizing adaptive on-time control topology. An on-demand modulation strategy and sleep-time detector are proposed to attain sub-μA quiescent current consumption under ultralight load condition. The adaptive-bias and adaptive-gain (A <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) comparator is presented to improve the loop stability caused by the inherent propagation delay of the low-power comparator. Moreover, a novel on-time generator is proposed to fix the switching frequency in continuous conduction mode. The proposed buck converter was implemented by using a 0.18-μm CMOS process with an area of 1.092 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It achieves a peak efficiency of 95.8% and >90% efficiency from 10 μA to 300 mA. A 240-nA quiescent current, including bandgap voltage and current reference, is achieved. With a low output ripple of less than 20 mV, the input voltage range and regulated output voltage are 2.1-5.5 and 1.8 V, respectively.

Improved Carbon Nanotube Field Effect Transistor for Designing a Hearing Aid Filtering Application

Designing a hearing aid device is one of the challenging applications recently, since it is useful for the people with hearing loss. For this purpose, various circuit designing procedures such as MOSFET and carbon nanotube field effect transistor (CNTFET) are introduced in the existing works. But it mainly lacks the following drawbacks: increased leakage current, not highly efficient, and increased area and power consumption. In order to mitigate these issues, this paper is aimed at designing an improved CNTFET (ECNFET) for hearing aid filtering application. The major objectives of the proposed work are leakage current minimization and the improvements in transconductance and mobility. At first, the layout is designed with 10 layers based on the specific dimensionalities, and different materials are placed in each and every layer. It includes gold, silicon, silicon dioxide, bismuth telluride, and carbon tube. Then, the parameters such as band gap, electron concentration, hole concentration, electron mobility, hole mobility, and insulator breakage voltage are verified to determine the efficiency of the layout. If all the parameters are satisfied, the characteristics such as voltage current, leakage current, mobility, and transconductance are validated. If all measures are satisfied, the library is created for the designed ECNFET layout by using the Comsol tool. Furthermore, the operational amplifier is designed based on the generated library function. After amplification, the hearing aid filter is designed with the use of the proposed ECNFET layout. The experimental validation of the proposed work and comparison with the existing method based on the measures of area consumption, power consumption, speed, and frequency range confirm the effectiveness of ECNTFET in filtering applications.

A 261mV Bandgap reference based on Beta Multiplier with 64ppm/0C temp coefficient

ABSTRACT In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/0C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm2 silicon area, with the nominal value of the reference at 261 mV.

A Chopper-Embedded BGR Composite Noise Reduction Circuit for Clock Generator

A chopper-embedded bandgap reference (BGR) scheme is presented using 0.18 μm CMOS technology for low-frequency noise suppression in the clock generator application. As biasing circuitry produces significant flicker noise, along with thermal noise from passive components, the proposed low-noise chopper-stabilized BGR circuit was designed and implemented for a wide range of temperature from −40 to 125 °C, including a startup and self-biasing circuit to reduce critical low-frequency noise from the bias circuitry and op amp input offset voltage. The BGR circuit generated a reference voltage of 1.25 V for a supply voltage range of 2.5–3.3 V. The gain of the implemented BGR operational transconductance amplifier is 84.1 dB. A non-overlapping clock circuit was implemented to reduce the clock skew effect, which is also one of the noise contributors. The noise analysis of a chopped bandgap voltage reference was evaluated through cadence periodic steady-state (PSS) analysis and periodic noise (PNoise) analysis. The low-frequency flicker noise was reduced from 1.5 to 0.4 μV/sqrt(Hz) at 1 KHz, with the proposed chopping scheme in the bandgap. Comparisons of the noise performance of the chopper-embedded BGR, with and without a low-pass filter, were also performed, and the results show a further reduction in the overall noise. A reduction in the flicker noise, from 181.3 to 10.26 mV/sqrt(Hz) at 100 KHz, was observed with the filter. All circuit blocks of the proposed BGR scheme were designed and simulated using the EDA tool HSPICE, and layout generation was carried out by Laker. The BGR architecture layout dimensions are 285.25 μm × 125.38 μm.

Computational engineering to enhance the photovoltaic by end‐capped and bridging core alterations: Empowering the future with solar energy through synergistic effect in D‐A materials

AbstractOrganic photovoltaic solar cells are being designed to offer a low energy photovoltaic (PV) solution. Optimizing the molecular backbone is one the most important technique for improving the photovoltaic characteristic of A‐D‐A type small active layer molecules. Herein, we have designed and theoretical characterized six new molecules by end‐capped and bridging core modifications of recently synthesized molecule BFHIC‐4F. Enhancement in photovoltaic, optoelectronic and physio‐chemical properties of newly designed molecules are seen by doing such modifications. Different advanced quantum chemical techniques have been employed to evaluate the performance of newly planned molecules. Large open circuit voltage and narrow band gap suggested that the designed molecules are efficient aspirants for solar cell applications. Moreover, maximum absorption capability in near‐infra‐red (NIR) region is observed for these newly designed molecules. To sum up, outcomes of all analyses advocated that the designed molecules are efficient candidates for solar cell applications.

An ultralow-power CMOS bandgap voltage reference with N+ doped PMOS

An ultra-low-power and low-area complementary metal oxide semiconductor (CMOS) bandgap voltage reference, without resistor and substrate bipolar, is presented and verified in the TSMC 0.18 μm CMOS process in this paper. By adopting PMOS transistor with N+ doped gate and a new temperature compensation technique, the proposed bandgap demonstrates a power consumption of around 50 nA for a supply voltage of 1.5 V and a temperature coefficient of 75 ppm without trimming. The chip can operate with a supply voltage from 1.2 V to 1.8 V and small area of the bandgap is around 0.001 mm2. The characteristic of the proposed voltage bandgap reference makes it suitable for ultralow-power low-area applications.

Structural transformation and phase change properties of Se substituted GeTe

GeTe1−xSex (0 ≤ x ≤ 1.0) alloys have been prepared both in bulk and thin film forms to study the effect of selenium (Se) substitution for tellurium (Te) on the phase change properties. It is observed that with increasing Se substitution in GeTe, the structure transforms from rhombohdral structure to orthorhombic structure. Rietveld Refinement analysis support the phase transformation and show that the short and long bond lengths in crystalline GeTe decrease with increasing Se substitution but the rate of reduction of shorter bond length is more than the longer bond length. The GeTe1−xSex thin films undergo amorphous to crystalline phase change when annealed at high temperatures. The transition temperature shows an increasing trend with the Se substitution. The contrast in electrical resistivity between the amorphous and crystalline states is 104 for GeTe, and with the Se substitution, the contrast increases considerably to 106 for GeTe0.5Se0.5. Devices fabricated with thin films show that the threshold current decreases with the Se substitution indicating a reduction in the power required for WRITE operation. The present study shows that the crystalline structure, resistance, bandgap, transition temperature and threshold voltage of GeTe can be effectively controlled and tuned by the substitution of Te by Se, which is conducive for phase change memory applications.

A novel tunable bandgap voltage and current reference generation circuit

This paper presents a CMOS based tunable bandgap voltage and current reference generation circuit. The proposed circuit is designed without using Bipolar Junction Transistors (BJTs) for Proportional-To-Absolute-Temperature and Complementary-To-Absolute-Temperature generation, thus eliminating the problem of implementing BJT in CMOS fabrication process. The proposed circuit is simulated in standard 180 nm CMOS technology. A constant reference voltage ( $$V_{ref}$$ ) from 850 mV to 1.14 V and a constant reference current ( $$I_{ref}$$ ) from 170 to 227 nA is generated for corresponding supply voltage ( $$V_{dd}$$ ) tuned from 1.5 to 2 V for low power applications with an extended temperature range from − 55 to 175 $$^{\circ }$$ C. The proposed circuit at $$V_{dd}$$ = 1.8 V has a Temperature Coefficient (TC) of 0.37 and 0.53 ppm/ $$^{\circ }$$ C for $$V_{ref}$$ and $$I_{ref}$$ respectively, with a total power consumption of 594 nW (at $$V_{ref}$$ = 1.02 V and $$I_{ref}$$ = 204.5 nA). A monte-carlo simulation of the design is done for 1000 samples. The monte-carlo simulation for $$\hbox {V}_{{ref}}$$ , $$\hbox {I}_{{ref}}$$ and TC is done across the $$\hbox {V}_{{dd}}$$ (i.e. $$\hbox {V}_{{dd}} = 2\,\hbox {V}$$ to 1.5 V).