Abstract
ABSTRACT In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/0C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm2 silicon area, with the nominal value of the reference at 261 mV.
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