Bandgap Reference Research Articles

A High-Precision Current-Mode Bandgap Reference With Low-Frequency Noise/Offset Elimination

This brief presents a low-noise, low-offset bandgap reference for the biomedical electronic systems application. In order to reduce the low-frequency noise and increase the accuracy, the low-frequency noise/offset elimination technique based on current-mode bandgap reference (BGR) is proposed. Besides, this BGR utilizes a proportional to absolute temperature (PTAT) resistor feedback technique to minimize the low-frequency noise and offset from the current mirror. The proposed BGR is implemented in a 180 nm deep n-well CMOS process occupying an active area of 0.0725 mm2. The measured results indicate that the BGR outputs 0.6 V voltage and consumes 69 μA current under 1.2 V supply voltage. It can achieve 3.5 μV(rms) noise from 0.1 to 10 Hz and a 0.21% DC accuracy.

Technology Dependency of TID Response for a Custom Bandgap Voltage Reference in 65 nm to 28 nm Bulk CMOS Technologies

Technology Dependency of TID Response for a Custom Bandgap Voltage Reference in 65 nm to 28 nm Bulk CMOS Technologies

Design of a High PSRR Low-pressure Bandgap Reference Source with Curvature Compensation

Based on the NUVOTON 0.35 μm BCD process, a low voltage bandgap reference with an input voltage of 5 V and output voltage of 0.6 V is designed in this paper. The traditional low-voltage bandgap reference output voltage has a large temperature coefficient and poor ability to suppress power supply fluctuations. In this paper, a circuit with high order compensation is proposed to reduce the temperature coefficient of the circuit, and a pre-regulated circuit is used to increase the power supply rejection ratio. The simulation results are at -30 °C∼130 °C. The output voltage of reference voltage is 947.5 μV, the temperature coefficient is 9.58 ppm/°C, and the power suppression ratio is -104.62 dB, which meets the design requirements of the power management chip.

A Reference Voltage Circuit Applied in High Precision Delta-Sigma ADC

A novel reference voltage circuit design which is applied in high-precision Delta-Sigma ADC is implemented. The proposed reference circuit exploits a high-gain class-AB OTA as the error amplifier, which improves the transient response characteristics, ensures loop stability, and does not increase additional power consumption. The design and simulation of the proposed reference voltage circuit are fabricated by SMIC.18 CMOS technology. The simulation results manifest that the temperature coefficient of the bandgap reference is 6.825 ppm/°C in the temperature range from -40°C to 125°C. The transient response of the proposed reference circuit takes about 13 ns to reach the precision demanded by the reference voltage. The Σ-Δ modulator with the designed reference voltage circuit applied has an effective number of bits (ENOB) of 18.1 bits, a signal-to-noise-ratio (SNR) of 111.2 dB, and a signal-to-noise-plus-distortion (SNDR) of 110.9 dB at 1MHz sampling frequency and 625 Hz input signal.

A Capacitorless LDO Regulator with Fast Feedback Loop and Damping-Factor-Control Frequency Compensation

A fast feedback loop (FFL) based on comparators is proposed in this paper. The FFL improves the transient response characteristics of the output-capacitorless low-dropout (OCL-LDO) regulator. When the load current switches between 1 mA and 100 mA with 1 μs edge time, the overshoot and undershoot are 33 mV and 37 mV, respectively, and recovery time is 1.2 μs and 1.6 μs, respectively. A damping-factor-control (DFC) frequency compensation circuit is used to ensure the stability of the OCL-LDO, and the simulation results show that the phase margin exceeds 50 degree in the entire load variation range. This design is based on 180 nm process, and the area of the chip is 0.068 mm2 (without pads). A band-gap reference circuit is also designed in this work; its output voltage is 1.2 V and its temperature coefficient is 7.96 ppm/∘C. The input voltage range of the proposed OCL-LDO is 2.5 V to 5 V with a linear regulation rate of 0.128 mV/V and a load regulation rate of 0.0017 mV/mA. In addition, the load range of the proposed OCL-LDO is 0 mA to 100 mA, and the minimum required external capacitance is 0 F. The power supply rejection ratio (PSRR) is −46 dB @ 1 kHz.

A high-accuracy voltage reference with high-order curvature compensation and base-current-canceling techniques

This paper presents a low dropout bandgap voltage reference circuit that combines high output voltage accuracy and low temperature-coefficient in a wide temperature range. The low temperature-coefficient is achieved by an advanced high-order curvature compensation technique, which is implemented by a novel exponential piecewise compensation term in a high-temperature range. A supply noise self-regulation technique is proposed to realize an excellent power supply rejection ratio (PSRR) without using any amplifiers in this paper. The proposed high-accuracy voltage reference is designed in a 2[Formula: see text][Formula: see text]m bipolar process. The circuit generates a reference voltage of 3.3[Formula: see text]V and can operate under a minimum supply voltage of 3.8[Formula: see text]V, while consuming 44.8[Formula: see text][Formula: see text]A. The output voltage accuracy is ± 0.15%. The PSRR at 10[Formula: see text]Hz and 1[Formula: see text]MHz is [Formula: see text][Formula: see text]dB and [Formula: see text][Formula: see text]dB, respectively. The line regulation is 2.45[Formula: see text]ppm/V in a supply voltage range from 3.8[Formula: see text]V to 20[Formula: see text]V. The average temperature coefficient is 11.9[Formula: see text]ppm/∘C in a temperature range from [Formula: see text]C to +125∘C.

Implementation of OTA in 90nm Technology with Bandgap Reference Application

Operational Transconductance Amplifier (OTA) is the basic building block of Analog circuit with linear input/output characteristics. Because it associates closely linked parameters like noise and settling performance, the current design methodologies for two-stage OTAs frequently result in sub-optimal solutions. The study discusses the implementation of an Operational transconductance amplifier (OTA) with a bandgap reference (BGR) circuit and its importance in providing a stable and accurate reference voltage for various analog and digital circuits. The combination of OTA and BGR provides a stable and accurate reference voltage that can be used in various analog and digital circuits. OTAs are used to drive high capacitive loads. To scale the dimensions of Complementary Metal Oxide Semiconductor (CMOS) technology requires proportional scaling, also taking supply voltage into consideration. In addition to the simplicity and strong performance that the Band Gap Reference (BGR) achieves as a load for the OTA circuit, the architecture of OTA with BGR as load is easily adaptable to attain high accuracy. Because the performance of the used amplifier has a significant impact on the OTA’s performance, consideration must be given to the design and its architecture. Therefore, it is essential to carry out a comparison analysis in order to get the optimal results of the outputs of OTA having BGR as the load.

A 54 µW CMOS Auto-Trimming Bandgap References (ATBGR) Achieving 90 dB PSRR for Artificial Intelligence of Things (AIoT) Chips.

An Auto-Trimming CMOS Bandgap References Circuit (ATBGR) with PSRR enhancement circuit for Artificial Intelligence of Things (AIoT) chips is presented in this paper. The ATBGR is designed with a first-order temperature compensation technique providing a stable reference voltage of 1.25 V in the ranges of input voltages from 1.65 V to 4.5 V. An auto-trimming circuit is integrated into a PTAT resistor of BGR to minimize the influences of the process variations. The four parallel resistor pairs with PMOS switches are connected in series with the PTAT resistor. The reference voltage, VREF, is compared to an external constant value, 1.25 V, through an operational amplifier, and the output of the de-multiplexer is used to configure the PMOS switches. High power supply rejection is achieved through a PSRR enhancement circuit constituting a cascaded PMOS common gate pair. The ATBGR circuit is fabricated in 180 nm CMOS technology, consuming an area of 0.03277 mm2. The auto-trimming method yields an average temperature coefficient of 9.99 ppm/°C with temperature ranges from -40 °C to 125 °C, and a power supply rejection ratio of -90 dB at 100 MHz is obtained. The line regulation of the proposed circuit is 0.434%/V with power consumption of 54.12 µW at room temperature.

A HCI self-healing circuit of a bandgap reference circuit with curvature compensation

In this paper, the performance degradation of a bandgap reference circuit with curvature compensation under the hot carrier injection (HCI) effect is studied, and a self-healing circuit is proposed. The intrinsic performance of the curvature compensation bandgap circuit achieved a temperature coefficient (TC) of 1.949 ppm/°C and an output reference voltage of 384.748 mV under a 1.2 V power supply voltage between −40 °C to 125 °C. The TC of the reference circuit will increase to 8.033 ppm/°C and the output reference voltage decreases to 384.318 mV after 50 years under the HCI effect. The study found that the gain decrease of the op-amp in the reference circuit leads to a decrease in the output voltage, and the decrease of the compensation current in the curvature compensation circuit leads to the degradation of the TC. A self-healing circuit is designed to mitigate the impact of the HCI effect. The simulation results show that the TC of the self-healing reference circuit is 3.934 ppm/°C and the output reference voltage is 384.655 mV after 50 years under the HCI effect.

A -80dB PSRR 1.166ppm/°C bandgap voltage reference with improved high-order temperature compensation

A -80dB PSRR 1.166ppm/°C bandgap voltage reference with improved high-order temperature compensation

Trimmable bandgap reference circuit with exponential curvature compensation

This paper proposes an improved exponential curvature-compensated bandgap reference circuit to exploit the exponential relationship between the current gain β of the bipolar junction transistor (BJT) and the temperature as well as reduce the influence of resistance-temperature dependency. Considering the degraded circuit performance caused by the process deviation, the trimmable module of the temperature coefficient (TC) is introduced to improve the circuit stability. The circuit has the advantages of simple structure, high linear stability, high TC accuracy, and trimmable TC. It consumes an area of 0.09 ​mm2 when fabricated by using the 0.25-μm complementary metal-oxide-semiconductor (CMOS) process. The proposed circuit achieves the simulated power supply rejection (PSR) of about −78.7 ​dB@1 ​kHz, the measured TC of ∼4.7 ​ppm/°C over a wide temperature range from −55 ​°C to 125 ​°C with the 2.5-V single-supply voltage, and the tested line regulation of 0.10 ​mV/V. Such a high-performance bandgap reference circuit can be widely applied in high-precision and high-reliability electronic systems.

A High-Precision Current-Mode Bandgap Reference with Nonlinear Temperature Compensation.

A high-precision current-mode bandgap reference (BGR) circuit with a high-order temperature compensation is presented in this paper. In order to achieve a high-precision BGR circuit, the equation of the nonlinear current has been modified and the high-order term of the current flowing into the nonlinear compensation bipolar junction transistor (NLCBJT) is compensated further. According to the modified equation, two solutions are designed to improve the output accuracy of BGR circuits. The first solution is to divide the NLCBJT branch into two branches to reduce the coefficient of the nonlinear temperature compensation current. The second solution is to inject the nonlinear current into the two branches based on the first one to further eliminate the temperature coefficient (TC) of the current flowing into the NLCBJT. The proposed BGR circuit has been designed using the Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that the variations in currents flowing into NLCBJTs improved from 148.41 nA to 69.35 nA and 7.4 nA, respectively, the TC of the output reference current of the proposed circuit is approximately 3.78 ppm/°C at a temperature range of -50 °C to 120 °C with a supply voltage of 3.3 V, the quiescent current consumption of the entire BGR circuit is 42.13 μA, and the size of the BGR layout is 0.044 mm2, leading to the development of a high-precision BGR circuit.

A novel curvature‐correction technique insensitive to process variations

AbstractThis paper proposes a novel curvature‐correction technique insensitive to process variations, which can be used in not only the bandgap reference (BGR) circuit but also the Zener reference circuit. By using two BJT transistors to form a differential pair structure, the current difference between the differential pair generates a compensation current, which compensates for the non‐linearity in the reference voltage. Unlike the classic curvature‐correction technique which can only be used in the BGR circuit, this novel technique can be used in the Zener reference circuit as well. What is more, the proposed curvature‐correction technique is insensitive to process variations, which greatly increases the reliability of commercial products. Finally, simulation results verify the validity of the proposed technique.

An Enhanced Anti-surge Circuit for New Energy Vehicle Electronics System

This paper presents an input surge protection circuit for automotive electronics systems with an adjustable overvoltage protection threshold suitable for high input voltage applications. Compared with the conventional overvoltage protection circuit, it boasts a new high-voltage bandgap reference circuit design without pre-regulation, which takes up less space and can be used on a limited PCB board, expanding the practical application range of the chip. The gate protection circuit can monitor the gate-source voltage of the power MOS in real-time and control the charge pump’s operating mode to improve the system’s safety. The design and simulation of the circuit adopt the 0.18 μm 5V/25V BCD process. The simulation results show that the bandgap reference voltage varies by only 0.38 mV in the input voltage range of 3.5 V-25 V. The quiescent current is 146 uA at 5 V supply voltage. The power MOS can be turned on quickly within 50 us. The overvoltage response time is 599 ns, permitting the circuit to be shut down when a surge occurs.

A 6.435-nW, 26.2-ppm/°C hybrid bandgap reference with stacked ΔVGS compensation in sub-threshold region

This paper illustrates a methodology to design an ultra-low power hybrid bandgap reference (HBR) with high accuracy to counteract the effect of temperature using single BJT and MOSFETs working in subthreshold region. Based on compensated VBE and ΔVth, the study provides a new insight into compensation of complementary-to-absolute-temperature (CTAT) voltage with a nano-watt proportional-to-absolute-temperature (PTAT) voltage generator with reduced threshold voltage-induced process variation. Designed in a 180 nm CMOS process, the circuit has a measured temperature coefficient of 26.2 ppm/°C with a wide temperature range of −40 °C∼125 °C and an overall variation coefficient of 0.234% among 9 chips with an active area of 0.0264 mm2. The experimental result shows that the proposed HBR circuit can operate with a supply voltage down to 1.1 V and a full frequency PSRR of better than −35 dB while the power consumption is only 6.435 nW.

A Comprehensive Study of Different Techniques for Voltage References

In the analog and mixed-signal integrated circuits, voltage references that are independent of various factors such as temperature drift, noise, supply voltage, etc., and efficient in terms of power as well as area, are highly in demand to improve the efficiency of the overall circuits. Voltage references are one of those circuits that have applications in both high-power systems and low-power system-on-chip (SoC) designs for wireless connectivity like the internet of the things (IoT) or the internet of the medical things (IoMT). They are responsible for providing a stable bias or reference voltage. Thus, voltage reference influences directly or indirectly the performance of these systems. A comparative study between the techniques used in bandgap voltage references and CMOS voltage references, in terms of performance parameters such as line sensitivity, output noise, PSRR, temperature coefficient, etc., is presented in this paper so that we can choose the voltage references as per the applications and environment.

Fully integrated multi-level non-overlapping clock phase generator for pipelined ADCs in SiGe BiCMOS 0.13 μm

This work presents a novel multi voltage level non-overlapping clock phase generation architecture with a differential clock driver. It has a compact fully integrated power management, including LDOs and bandgap reference circuit. It is capable of controlling the PVT variation via SPI programming. It is functional from 50 MHz up to 1 GHz, to be used for pipelined ADCs. The core chip achieves SNRjitter around 72 dB from 50 MHz to 150 MHz, and above 68 dB from 150 MHz to 400 MHz, above 60 dB up to 1 GHz clock signals. The core section consumes 19 mA at 1 GHz from an external supply of 3 V. The chip occupies 1235 μm × 1300 μm, in a SiGe BiCMOS 0.13 μm process. The clock generation system occupies 400 μm × 360 μm silicon area, excluding I/O pads and interface circuits. It is packed in a 5 mm × 5 mm QFN32 package and assembled onto an FR4 board.

A low temperature coefficient wide temperature range bandgap reference with high power supply rejection

This paper presents a low temperature coefficient and wide temperature range bandgap reference with high power supply rejection. High temperature curvature compensation of this circuit is accomplished by MOSFET transistors operating in the subthreshold region. With the proposed piecewise compensation technique, the temperature range is extended. At the same time, a pre-regulator structure is adopted to improve the line sensitivity and suppress the ripple of the power supply. The novel bandgap reference is proposed and verified in 180nm CMOS process. The measured is 1.18V at 3.3V power supply voltage, and the static current of the circuit is 75uA. Over the wide temperature range of -60∼160◦C, the temperature coefficient achieves 5.72ppm/◦C, and the power supply rejection is -93.26dB at low frequency.

A fully integrated ultra-low noise low-dropout regulator inherently combined with bandgap reference for SoC applications

This paper presents a capacitor-less ultra-low noise low-dropout regulator (LDO) inherently combined with bandgap reference (BGR). Compared to traditional LDOs with a dedicated error amplifier (EA) followed by a BGR to generate a variety of desired output voltages through power transistors, the proposed LDO uses a novel architecture, which employs a BGR inherently combined with LDO sharing the same operational amplifier (OPA) for the voltage generation. By doing so this architecture not only reduces LDO’s power consumption and design complexity, but also greatly improves its low-frequency noise characteristic due to much less noise contribution from the active part of EA. The design procedure of the proposed LDO is presented with its implementation in the 40 nm CMOS process. The post-simulation results show that the output voltage ranges from 1.27 V to 2.67 V at a power supply of 3.3 V, with an average temperature coefficient (TC) of 11.9 ppm/°C over a temperature range (TR) of −40 °C to 125 °C. With an LDO output voltage of 1.27 V and a load current of 10 mA, the output noise is as low as 2.61 μV/Hz at 1 Hz and the integrated noise is 5.09 μVRMS from 1 Hz to 100 Hz. The quiescent current is only 30 μA in standby mode. The proposed LDO occupies an area of 0.036 mm2. This ultra-low noise LDO is quite suitable for low-frequency signal conditioning circuit and system design, such as Doppler radar transceivers and bio-medical circuit and system.

A Low Phase Noise Crystal Oscillator with a Fast Start-Up Bandgap Reference for WLAN Applications

This article presents the design and implementation of a 40 MHz crystal oscillator (XO) with low phase noise, based on the 55 nm CMOS process, for wireless transceiver systems, particularly those used in Wireless Local Area Network (WLAN). The proposed design employs a bandgap reference circuit that includes a start-up circuit and a low-voltage common-source common-gate current mirror, which ensures that the bandgap reference circuit is powered up effectively across all temperatures and process corners. A low-pass filter is also incorporated at the low dropout regulator (LDO) input to reduce the phase noise of the XO circuit. The experimental results demonstrate that the proposed design achieves a final phase noise of −164.36 dBc/Hz at 100 kHz offset frequency, with a power consumption of 0.444 mW. The test of start-up time is 0.718 ms and the compact chip area is 0.088 mm2. According to the simulation and test results, the final FOM value calculated in this paper is 209.93 dBc/Hz at 100 kHz offset.