Balun Low Noise Amplifier Research Articles

A 1.46–1.96-dB-NF 2.1–5.2-GHz Wideband Passive Balun LNA in 22-nm CMOS

This brief presents a CMOS wideband passive balun low noise amplifier (LNA) based on magnetically coupled resonator (MCR) matching network. The theoretical analysis, expression derivation and simulation verification of the impedance rise with frequency of MCR matching network is presented for the first time. The proposed wideband LNA was fabricated in 22-nm CMOS technology, which achieves a maximum power gain of 15.7 dB, noise figure (NF) of 1.46-1.96 dB. The 3-dB bandwidth ranges from 2.1-5.2 GHz. The minimum power input at 1dB compression point (IP1dB) is -15.2 dBm. The LNA core area is 0.38 mm2 and dissipates a total power of 16 mW from 1 V power supply.

A Broadband High Gain, Noise-Canceling Balun LNA with 3–5 GHz UWB Receivers for Medical Applications

The Ultra-Wideband Wireless Body Area Network (UWB-WBAN) has been identified to provide an efficient, low-power, and improved wireless communication between sensor nodes worn by the human body to monitor physiological signals. The first part of the UWB receiver is a low noise amplifier (LNA). This article describes an upgrade to a sort of balun LNA that is entirely transistor-based and devoid of inductors for medical worn communication service. The balun LNA uses common gate and a common source configuration which cancels the noise generated by the common gate. This work uses the transistors in place of resistors to minimize the integrated circuit's area, as well as finding the best values for the dimensions of the transistor to minimize energy consumption, achieve a high gain and good linearity. This reduces the noise figure. The designed system utilizes the UWB frequency range of 3-5 GHz and a voltage supply of 1.8V. The designed balun LNA is able to achieve a peak gain of 25.5 dB and noise figure (NF) less than 3.2-3.5 dB using 180µm TSMC CMOS technology. The IIP3 is quite high at 2 dBm, whereas the IIP2 maximum is 21 dBm. The entire power consumption is less than 7.2 mW.

A Sub-1-GHz Band High-Dynamic-Range Receiver With Integrated Self-Adaptive Multipart AGC Loops

This article presents a fully differential high-dynamic-range direct-conversion receiver for sub-1-GHz band applications in a 180-nm CMOS technology. The integrated self-adaptive multipart automatic gain control (AGC) loops are designed to cope with large input signal. In the radio frequency (RF) domain, a gain-adjustable noise-canceling balun low-noise amplifier (LNA) and a high-linearity RF variable gain amplifier (VGA) are co-designed to keep a steady differential output power for the mixer stage. In baseband (BB), a novel gain distribution method is proposed to protect BB circuits from saturation. To prove the concept, one of the most typical and strict application scenarios in the sub-1-GHz band, digital television (DTV) standard, is analyzed and chosen as the design target. The receiver achieves a noise figure (NF) of 3.6–4.6 dB in the ultrahigh-frequency (UHF) band. A wide gain tuning range of 128.8 dB is realized in this work, featuring fully integrated AGC loops. The programmable bandwidth of the low-pass filter (LPF) can be adjusted from 1 to 4 MHz, supporting 2-/6-/7-/8-MHz signal channels. The maximum in-band third-order input-referred intercept point (IIP3) is 10 dBm under the conversion gain of 0 dB. The receiver consumes 49.56 mA from a 1.8-V voltage supply and occupies an area of 3.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS

A low power receiver is designed and implemented for 2.4 GHz Industrial-Scientific-Medical (ISM) band in a 40 nm CMOS process. To obtain good noise and linearity performance at low cost, a current-reused low power inductor-less balun low noise amplifier (LNA) structure is proposed without use of monolithic spiral inductors or transformers. The receiver adopts a zero-IF architecture and current mode mixing operation which avoid need of large voltage headroom for the radio frequency (RF) voltage swing under strong interferers. A third order active-RC low pass filter (LPF) with RC calibration and DC offset cancelation (DCOC) blocks are carefully designed. Current reusing technique and timing optimized asynchronous SAR logic are adopted in LNA and ADC design respectively, featuring high-power efficiency. The total receiver chain achieves maximum conversion gain of 80.32 dB, noise figure (NF) of 6.27 dB and input referred third-order intercept point (IIP3) of −0.6 dBm with 32.8 mW power consumption.

Performance of ultra‐wide band DCBLNA with suspended strip line radiator for human breast cancer diagnosis medical imaging application

This study presents the performance of differential cascode balun low noise amplifier (DCBLNA) with ultra-wideband (UWB) for human breast cancer diagnosis. The proposed DCBLNA design-I with bulky spiral inductors achieves insufficient bandwidth with large power consumption of 10.8 mW. To attain the proper UWB band of operation, suspended strip line (SSLIN) radiators have employed in the proposed design-I. The performance of SSLIN is evaluated in terms of line capacitance and characteristic impedance by optimising its width. It is observed that best 50 Ωn-II. DCBLNA design-II using SSLIN have achieving a desired band of operation ranging from 1.5 to 15.7 GHz and best NF of 0.5 dB. The gain and phase imperfections are simulated to characterise balun networks. The smallest gain imperfection achieved is 0.1 dB at 10 GHz while the simulated phase imperfection turns out to be sufficiently good with 2.35° at 8 GHz. The proposed DCBLNA design-II is implemented and fabricated using RFCMOS 45 nm Taiwan Semiconductor Manufacturing Company (TSMC) process under commercial conditions. The highest figure of merit comes out to be 3.2 that ensures good accuracy of medical imaging for breast cancer diagnosis.

Low‐power inductorless wideband SFBB balun low noise amplifier with noise reduction and third‐order transconductance optimization

AbstractThis article presents an inductorless wideband balun low noise amplifier (LNA), which uses noise reduction and linearity optimization techniques at low supply voltages. The proposed self forward body biased LNA uses inverter type amplifier structure as input stage for impedance matching while output stages are noise reduction stages, which partially cancel the noise of the input stage. In addition to noise reduction, transistors are biased near‐zero third‐order transconductance region to maximize third‐order input‐referred intercept point (IIP3) performance at low supply voltages. The LNA, implemented in 180 nm RFCMOS technology, is evaluated at 1 and 0.9 V supply voltages to show low voltage operation. It shows a maximum voltage gain of 19.7 dB with a minimum noise figure of 2.7 dB and a maximum 3‐dB bandwidth that spans from 300 MHz to 1.83 GHz. The minimum achieved IIP3 at 0.9 V supply voltage is −1.7 dBm. The circuit draws a maximum current of 10.36 mA from 1 V power supply and occupies an area of 0.08 mm2.

Balun LNA Thermal Noise Analysis and Balancing With Common-Source Degeneration Resistor

The Balun low noise amplifier (LNA) is an LNA that exploits a combination of a common-source (CS) and a common-gate (CG) transistors, which cancels the noise and distortion of the CG stage. And since the CG is known to be linear, only the CS needs to be carefully designed and optimized. The Balun LNA also cancels the distortion and noise of the CG. In this paper, the CS section will be fully analyzed, and shown how the condition set in the literature review still satisfy the balancing output and cancel the CS stage thermal noise as well as the CG thermal noise. Also, forward body biasing (FBB) is used to reduce the threshold voltage and an addition of CS degeneration resistor to balance the output while still canceling the thermal noise of the transistors is tested using UMC180nm on Cadence. The LNA achieves a gain of 19-16dB, NF < 3.6 over the bandwidth 200M-1.9GHz without a CS degeneration. A 17.8-14.8dB gain, a NF < 3.8 over the bandwidth 200MHz-2.1GHz and power consumption of 12mW in both cases. Although outside the bandwidth, at ISM 2.4GHz a gain of 14.5dB and a NF of 3.8 is achieved, making it suitable for wireless sensor node (WSN) applications. According to the author’s knowledge, this is the first time the degeneration resistor noise analysis on a Balun LNA is derived and analyzed.

A 60 GHz balun low-noise amplifier in 28-nm CMOS for millimeter-wave communication

In this paper, a 60 GHz complementary metal-oxide-semiconductor (CMOS) balun low-noise amplifier (LNA) was implemented for millimeter-wave communication. To improve the gain and noise performance, slow-wave coplanar waveguides (S-CPW) with high quality factor were designed as input, output, and inter-stage matching networks. At the input port, a balun transformer provides additional passive gain while performing the singled-ended to differential conversion. Implemented in a 28-nm CMOS process, simulated results show that the proposed LNA exhibits a simulated linear gain of 16 dB and a noise figure of 5.6 dB at 60 GHz, with a 3-dB gain bandwidth of 5 GHz (58 GHz–63 GHz). The input return loss is better than −25 dB at the central frequency. The simulated input third-order intercept point (IIP3) is −5 dBm. The circuit draws 35 mA from 1 V supply voltage.

Design and integration of a high gain low NF CG-Folded cascode inductorless balun-LNA with loaded on-chip loop antenna

In this paper, a novel inductorless CG-Folded Cascode balun-low noise amplifier (balun-LNA) for 2.4 GHz biomedical receivers is proposed and integrated to a reactively loaded on-chip loop antenna through capacitive on-chip matching network. On-chip antenna has small feed point resistance at 2.4 GHz, hence LNA can be designed for a lower input resistance than the conventional 50 Ω. The single input balun-LNA has balanced differential outputs such that for lower input impedance, the gain and noise figure (NF) are improved. Folded cascode topology improves voltage swing and linearity. Communication range is computed by designing a power amplifier (PA) and two-turn on-chip antenna at transmitter side. Post-layout simulations of LNA, matching network and PA designed in UMC 180 nm technology are carried out using Cadence Virtuoso. LNA has a simulated gain of 21.3 dB, NF of 1.6 dB and IIP3 −1 dB, matching network has S11 of –23 dB and PA has an output power 18dBm. On-chip transmit and receive antennas designed in Advanced Design System (ADS) have a gain of −20.6 dBi and −16.7 dBi. Compared to reported LNAs integrated with on-chip antennas below 12 GHz, the proposed design has low power consumption of 2.3 mW, higher FoM, small size of 0.65 mm2 and achieves computed inter-chip communication range of 2.3 m with the designed transmitter.

High-gain inductorless Wideband Balun-LNA using asymmetric CCC & BIST using RMS detectors

In this paper, an inductorless wideband balun-low noise amplifier (LNA) using current source loads, common-mode feedback (CMFB), asymmetric capacitive cross-coupling (CCC) and auxiliary common-source amplifier are proposed to obtain low noise figure (NF) and high gain. The asymmetric CCC boosts the gain and reduces the NF. The CMFB fixes the output to a common mode voltage. RMS detectors are proposed to realize a low-cost built-in self-test (BIST) circuit for measuring the gain of the LNA during its entire lifespan. The proposed balun-LNA is implemented in 0.18 µm CMOS process technology and the performance is studied through post-layout simulations. PVT and Monte Carlo simulations are performed to check for the robustness and yield of the circuit. From these analyses, it is found that the integrated average gain of the LNA obtained with and without the RMS detectors is 19.1 dB and 20.1 dB respectively in the 3 dB-band of 0.18–2 GHz. NF of the LNA in this band is 2.87 dB. The average IIP3, IIP2, and 1 dB compression points of the LNA are (−4.89 dBm, +28.57 dBm, −20.42 dBm) respectively. The proposed LNA dissipates a power of 4.9 mW with a supply of 1.2 V and requires an area of 0.04 mm2.

Inductor-less PVT robust gain switching balun LNA for multistandard applications

ABSTRACTAn inductor-less single to differential low-noise amplifier (LNA) is proposed for multistandard applications in the frequency band of 0.2–2 GHz. The proposed LNA incorporates noise cancellation and voltage shunt feedback configuration to achieve minimum noise characteristics and low power consumption. In addition to noise cancellation, trans-conductance of common-source stage is scaled to improve the noise performance. In this way, noise figure (NF) of LNA below 3 dB is achieved. An additional capacitor Cc is used to correct the gain and phase imbalance at the output. The gain switching has been enabled with a step size of 4 dB for high linearity and power efficiency. The bias point of all transistors is chosen such that the variation in gm is not more than 10%. The proposed LNA is implemented in UMC 0.18-μm RF CMOS technology. The core area is 182 μm × 181 μm. Moreover, the LNA has better ratio of relevant performance to area. The proposed balun LNA is validated by rigorous Monte Carlo simulation. The 3σ deviation of gain and NF is less than 5%. Finally, the proposed LNA is robust to unavoidable PVT variations.

A wideband noise cancelling balun LNA employing current reuse technique

A balun inductorless wideband low noise amplifier (LNA) with active loads is proposed for multi-standard radio applications. The noise cancelling and current reuse techniques are combined to mitigate the need for high power consumption in conventional balun LNAs. This adds a degree of freedom for transconductance of common gate stage (gmCG). As a result, lower gmCG without degrading the input matching, allows a large scaling factor for common source (CS) stage in noise cancelling technique. Post-layout simulation results of the proposed LNA circuit in a 180 nm RF CMOS process show voltage gain of 20.2 dB, −3 dB bandwidth from 600 MHz to 3.15 GHz. The minimum NF is 2.37 dB with input return loss (S11) better than −13 dB in all frequency range and third input intercept point (IIP3) is −2.1 dBm. The circuit dissipates 6 mW from 1.5 V DC supply with an active area of 0.026 mm2.

PVT compensated high selectivity low‐power balun LNA for MedRadio communication

A single-to-differential low-noise amplifier (LNA) is proposed for low-power medical devices in the frequency band of 401-406 MHz. The proposed LNA avoids the use of surface acoustic wave (SAW) filter and additional balun in RF receiver front-end. The LNA comprises inductive degeneration common source (IDCS) technique (stage I) and a cascaded common source circuit (stage II). The stage-II is stacked on top of stage-I. The proposed balun LNA incorporates single to differential (SD) conversion for minimum gain and phase error. A compensation bias circuit is proposed to minimise variations in parameters of LNA against process corners, supply voltage and temperature (PVT). An upsurge balun LNA is designed in UMC 0.18-μm CMOS technology, the DC power consumption is 290 μW under a supply voltage of 1 V and the minimum noise figure is 3 dB. The die area of LNA including buffers and bias circuit is 850 μm × 978 μm. The worst-case post layout simulation results show a gain and phase error of 0.8 dB and 10°. The percentage variation of gain and NF against PVT is reduced by 55 and 48%. Furthermore, the balun LNA has out of band rejection at the roll-off rate better than 70 dB/dec.

A Wideband Low-Power-Consumption 22–32.5-GHz 0.18- $\mu \text{m}$ BiCMOS Active Balun-LNA With IM2 Cancellation Using a Transformer-Coupled Cascode-Cascade Topology

A low-power-consumption wideband 0.18- $\mu \text{m}$ BiCMOS active balun-low noise amplifier (LNA) with linearity improvement technique for millimeter-wave applications is proposed. The linearity technique utilizes constant Gm transconductance structure with the second-order intermodulation (IM2) cancellation that provides robustness to input and output variations. The constant Gm is established with equal emitters’ area ratios and proper base-emitter biasing voltage, thus improving linearity. Furthermore, power saving is achieved using inductive coupling boosting the overall Gm structure and reducing the current consumption for the auxiliary gain stage. The measured balun-LNA’s power gain between the input and two outputs is 15.4 and 15.6 dB with input return loss greater than 8.7 dB. The gain and phase mismatches are less than 1.8 dB and 12°, respectively. The balun-LNA noise figures between the input and two outputs are less than 5.5 and 6 dB at 32.5 GHz. The measured input points [referred 1-dB gain compressions ( $P_{\mathrm {{in}}}1$ dB’s), input referred third-order intercept IIP3’s] and the input referred second-order intercept points (IIP2’s) are more than −14.6, −5.7, and 42 dBm across 22–32.5 GHz, respectively, and the total power consumption is less than 9 mW drawn from 1.8 V power supply.

Low power ultra wide-band balun LNA using noise cancellation and current-reuse techniques

A low power, single to differential (balun) low noise amplifier (LNA) using noise cancellation and current re-use techniques is presented for ultra wide-band applications. An upsurge balun LNA is designed using UMC 0.18-μm RF CMOS technology with an emphasis on the covenant between gain, bandwidth and power dissipation. The proposed balun exerts a differential stage on top of common gate-common source (CG-CS) stage. A CG-CS stage exploits amalgamation of CG stage (for wide-band impedance matching) and CS to curtail gain and phase imbalance, while simultaneously negating the noise and distortion of input matching transistor. The escalation of bandwidth has been accomplished using staggered tuning on CG-CS and differential stages. The stacked differential amplifier does cancellation of self noise as well as supply noise. The proposed UWB balun LNA achieves 14dB voltage gain with agreeable input reverse isolation (S11) of <-8dB over the frequency range of 3.19–8.8GHz. The minimum noise figure of 3.9dB and P1dB of −10.5dBm while exhausting 3.8mW from 1.2V supply. The superlative performance of balun LNA is accomplished between 3.19 and 8.8GHz with gain and phase errors below 0.2dB and 0.40 respectively. The layout occupying 0.77mm2 area. The overall pre and post layout simulations of proposed LNA shows admissible agreement with theoretical predictions.

RF low power subsampling architecture for wireless communication applications

With the increasing demands of wireless communication, flexible, complex, and diversified wireless communication applications are required. However, the difficulty of enabling new wireless communication applications is the lack of low power radio frequency (RF) transmission devices, especially the RF receiver. In order to alleviate this problem, an RF low power subsampling architecture for wireless communication applications is proposed in this paper. This subsampling architecture adopts a single-ended to differential configured balun low noise amplifier (balun-LNA), a subsampling mixer with high sampling ratio and a finite input response (FIR) filter and infinite impulse response (IIR) filter achieving frequency down-conversion, avoiding using high power-hungry blocks. Based on a subsampling theory, an optimum sampling frequency for the subsampling architecture is necessary to relax the complexity of the system. For the application of internet of things (IoT) wireless communication, the paper provides the implementation of the subsampling receiver solutions to get a tradeoff between power consumption, gain, noise, and sensitivity. It can achieve −85 dBm sensitivity for an amplitude shift keying (ASK) modulation at the data rate of 1 Mbps with the clock sampling frequency of 40 MHz. Finally, the theoretical analysis and simulation results show that the performance of the subsampling architecture has several advantages over others.

Noise canceling LNA with gain enhancement by using double feedback

In this paper we present a balun low noise amplifier (LNA) in which the gain is boosted by using a double feedback structure. The circuit is based on a conventional balun LNA with noise and distortion cancelation. The LNA is based on the combination of a common-gate (CG) stage and common-source (CS) stage. We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with a 130nm CMOS technology, show that the gain is 24dB and the NF is less than 2.7dB. The total power dissipation is only 5.4mW (since no extra blocks are required), leading to a figure-of-merit (FOM) of 3.8mW−1 using a nominal 1.2V supply. Measurement results are presented for the proposed DFB LNA included in a receiver front-end for biomedical applications (ISM and WMTS).

High linearity 24 dB gain wideband inductorless balun low-noise amplifier for IEEE 802.22 band

A 50 MHz---1 GHz low-noise amplifier circuit with high linearity for IEEE 802.22 wireless regional area network is presented. It was implemented without any inductor and offers a differential output for balun use. Noise canceling and linearity boosting techniques were combined to improve the amplifier performance in such a way that they can be separately optimized. Linearity was improved using diode-connected transistors. The amplifier was implemented in a 130 nm CMOS process in a compact 136 μm × 71 μm area. Simulations are presented for post-layout schematics for two classes of design: one for best linearity, another for best noise figure (NF). When optimized for best linearity, simulation results achieve a voltage gain >23.7 dB (power gain >19.1 dB), a NF 3.3 dBm (7.6 dBm max.) and an input power reflection coefficient S11 24.7 dB (power gain >19.8 dB), a NF ?0.3 dBm and an S11 <?11 dB. Monte Carlo simulation results confirm low sensitivity to process variations. Also a low sensitivity to temperature within the range ?55 to 125 °C was observed for Gain, NF and S11. Power consumption is 18 mW under a 1.2 V supply.

A LOW POWER 2.4 GHz RF TRANSCEIVER FOR ZIGBEE APPLICATIONS

This paper presents a low power RF transceiver for 2.4 GHz ZigBee applications. The current reused inductor-less-load balun low noise amplifier (LNA) with quadrature mixer is proposed for area and power saving for low-IF receiver. The transmitter adopts power efficient power amplifier (PA) to improve transmitting efficiency. This RF transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves 6.5 dB noise figure (NF) and 20 dB conversion gain. The transmitter delivers maximum +3 dBm output power with PA efficiency of 30%. The receiver and transmitter front-end dissipate 1.9 mW and 5.3 mW at 1.8 V supply, respectively. The whole die area is 0.95 mm2.