RF low power subsampling architecture for wireless communication applications

Fanzhen Meng,Mingliang Wang,Tong Tian,Xiaolin Zhang,Hong Liu

doi:10.1186/s13638-016-0627-z

Abstract

With the increasing demands of wireless communication, flexible, complex, and diversified wireless communication applications are required. However, the difficulty of enabling new wireless communication applications is the lack of low power radio frequency (RF) transmission devices, especially the RF receiver. In order to alleviate this problem, an RF low power subsampling architecture for wireless communication applications is proposed in this paper. This subsampling architecture adopts a single-ended to differential configured balun low noise amplifier (balun-LNA), a subsampling mixer with high sampling ratio and a finite input response (FIR) filter and infinite impulse response (IIR) filter achieving frequency down-conversion, avoiding using high power-hungry blocks. Based on a subsampling theory, an optimum sampling frequency for the subsampling architecture is necessary to relax the complexity of the system. For the application of internet of things (IoT) wireless communication, the paper provides the implementation of the subsampling receiver solutions to get a tradeoff between power consumption, gain, noise, and sensitivity. It can achieve −85 dBm sensitivity for an amplitude shift keying (ASK) modulation at the data rate of 1 Mbps with the clock sampling frequency of 40 MHz. Finally, the theoretical analysis and simulation results show that the performance of the subsampling architecture has several advantages over others.

Highlights

Thanks to the evolvement of the CMOS technology, the radio frequency (RF) integrated circuits can improve integration and reduce chip area greatly
The frequency conversion of RF subsampling receiver is shown in Fig. 2; RF signal is transferred to low intermediate frequency fIF by a proper local sampling frequency fs [13], and further converted to baseband
After a sample and hold (S/H) mixer, the intermediate frequency fIF is classified into I path SI,M and Q path SQ,M by the odd I path samples and the even Q path samples, respectively, which can further reduce the sampling rate and relax the complexity of A/D converter (ADC)

Summary

Introduction

Thanks to the evolvement of the CMOS technology, the RF integrated circuits can improve integration and reduce chip area greatly. In terms of sensitivity and integration of the system, the balunLNA based on the inductively degenerated structure is used to achieve high voltage gain and low noise figure It adopts the common-gate and commonsource cascade topology to provide differential output signal. High sampling frequency with low sampling ratio used to down-convert RF signal to intermediate frequency or baseband, which can increase the complexity and power consumption of the system [22]. Some new techniques, such as high Q filter and high sampling ratio, can be used to achieve high sensitivity, high integration, low noise, and low power consumption for the subsampling architecture [23]. In order to further improve the sensitivity and reduce the power consumption of the receiver, high sampling ratio and high Q filter can be used in the subsampling receiver. Taking the above problems into consideration, the detail analysis for the RF subsampling architectures should be introduced

RF subsampling architecture and theory

Voltage sampling and charge sampling

Subsampling architecture and circuits design

Findings

Conclusions