Backside Of Silicon Wafer Research Articles

Study of silicon chip soldering in high-power transistor housing

The aim of this work is to study the possibility of reducing the labor consumption and cost of high-power silicon transistor manufacturing without compromise in transistor low thermal resistance. To this end we experimentally explored replacing Au-Si solder with lead-silver solder or other solders for silicon chip soldering in transistor housings. This will reduce gold consumption and increase the efficiency of high-power transistor silicon chip installation due to the use of batch soldering technology. We also studied the effect of different silicon wafer back side treatment and thinning methods on the thermal resistance of the transistors. To improve the soldering quality we applied preliminary Ti–Ni metallization of the reverse side of the silicon wafer.We experimentally assessed the effect of outer housing layer materials and back side chip metallization. For lead-silver soldering of silicon chips, the best housing is that with a nickel outer layer rather than with a gold-plated one, because the resultant thermal resistance is lower and the absence of gold makes the technology cheaper. We obtained a 0.6K/W thermal resistance for a 24mm2 chip area.

Studies of SERS efficiency of gold coated porous silicon formed on rough silicon backside

Starting from a rough backside of silicon wafer, we have formed a porous layer by electrochemical anodization and then coated by a thin film of gold. The morphological characteristics of the porous silicon and in turn the metal film are governed by the anodization process and also by the starting surface. So, in order to investigate the Plasmonic aspect of such rough surface which combines roughness inherent to the porous nature and that due to rough starting surface, we have used a dye target molecule to study its SERS signal using a porous silicon layer obtained on the rough backside surface.The use of unusual backside of silicon wafer could be, beside the others, an interesting way to made SERS effective substrate thanks to reproducible rough porous gold on porous layer from this starting face. The morphological results correspond to the silicon rough surface as a function of the crystallographic orientation showed the presence of two different substrate structure. The optical reflectivity results obtained of gold deposited on oxidized porous silicon showed a dependence of its Localized Surface Plasmon band frequency of the deposit time. SERS results, obtained for a dye target molecule (Rhodamine 6G), show a higher intensities in the case of the 〈110〉 orientation, which characterized by the higher roughness surface. Voici “the most relevant and important aspects of our work”.

Preparation of hollow out-of-plane hafnium oxide microneedle arrays for transdermal drug delivery

Due to the incapacity of many drugs to enter the skin at therapeutically useful rates, transdermal drug delivery with the advantages of controlled release, high safety and low degree of side effects is seriously hampered in efficiency and success. A microneedle approach can dramatically promote transdermal delivery, especially for macromolecules. In this paper, a fabrication process for hollow out-of-plane hafnium oxide microneedles on silicon wafer using only one mask has been developed. Photoresist is spun on a 4ź silicon (100) wafer and patterned by a mask. Deep reactive ion etching is used to form deep molds inside the wafer. A hafnium oxide film is deposited by atomic layer deposition to cover the top side of the wafer and the inside walls of the molds. Then the back side of silicon wafer is etched under the condition of 30 wt% KOH solution and a water-bath temperature of 81 °C until exposed hollow hafnium oxide microneedles are obtained. Compared to the processes that have been developed for silicon, silicon oxide, or polymer microneedles, the process presented here is simpler, and the strength and flexibility of hollow hafnium oxide microneedles can be easily adjusted by modifying the depositing time of hafnium oxide films. Hafnium oxide microneedles have potential applications in transdermal drug delivery.

Selective dual-side functionalization of hollow SiO2 micropillar arrays for biotechnological applications

We report a method for the fabrication and selective functionalization of the internal and external surfaces of high-aspect-ratio hollow silicon dioxide (SiO2) micropillar arrays. The strategy enables independent surface reactions with no cross-contamination. The dual-functionalization is carried out during the fabrication of the micropillars in four steps. First, a sample of macroporous silicon is prepared by electrochemical etching and then it is thermally oxidized to create a thin layer of silicon dioxide on the internal surface of the macropores. Next, the internal surface is functionalized with mercaptopropyl trimethoxysilane (MPTMS). Subsequently, the micropillars are released by etching the back side of silicon wafers using a solution of tetramethylammonium hydroxide (TMAH). Finally, the external surface of the micropillars is chemically modified in a multi-step biofunctionalization with aminopropyl triethoxysilane (APTES), glutaraldehyde (GTA) and bovine serum albumin (BSA). The resulting structures were characterized by scanning electron microscopy and the surface reactions were confirmed by Fourier-transform infrared spectroscopy. The internal and external sides were photolabeled with tetramethyl rhodamine-5-maleimide and fluorescein isothiocyanate (FITC), respectively, and analyzed using fluorescence confocal microscopy. The peculiar three-dimensional (3D) geometry of the micropillars allows these double-active surfaces to be imaged at the same time. Results demonstrated the successful dual-side chemical modification and the feasibility of imaging both internal and external sides. Due to its remarkable architecture and chemical versatility, these micropillar arrays are a promising engineered platform for a range of applications such as biosensing, 3D cell culture and drug delivery.

Chemical Wet Etching of Silicon Wafers from a Mixture of Concentrated Acids

Warpage on the backside of silicon wafer after thinning process is examined. The thinning process includes back-grinding (BG) and wet chemical etching (WCE). Results of wafer warpage were compared to sub-surface damage from Transmission Electron Microscopy (TEM) analysis and showed that sub-surface damage on the backside of the silicon 100 would induce high wafer warpage, and reduced wafer strength. Further studies from surface roughness and topography of each surface finish is obtained by Atomic Force Microscopy (AFM) and SEM show that low surface roughness is in accordance with smooth surface condition, which comes after the wet etching process.

Micromachined Silicon Grids for Direct TEM Characterization of Carbon Nanotubes Grown by CVD

ABSTRACTTransmission electron microscopy (TEM) is a key technique in the structural characterization of carbon nanotubes. For device applications, carbon nanotubes are typically grown by chemical vapor deposition (CVD) on silicon substrates. However, TEM requires very thin samples, which are electron transparent. Therefore, for TEM analysis, CVD grown nanotubes are typically deposited on commercial TEM grids by post-processing. This procedure has two problems: It can damage the nanotubes, and it does not work reliably if the nanotube density is too low. The ability to do TEM directly on as-grown nanotubes lying on the silicon substrate would solve these two problems. In this work, for this purpose, we have fabricated micromachined TEM grids from silicon substrates. In particular, we have wet-etched large membranes from the back side of silicon wafers with a thin layer of thermal oxide on them. We have then etched a large array of long and narrow open slits on these membranes from the top side using a deep silicon etcher. Subsequently, we have grown nanotubes on these micromachined TEM grids by CVD, and characterized the nanotubes by high resolution TEM (HRTEM), micro-Raman spectroscopy, scanning electron microscopy (SEM), and atomic force microscopy (AFM). Since the nanotubes grown on the micromachined substrates are completely suspended over the width of the open slits, these substrates form a natural TEM grid for direct imaging of CVD-grown nanotubes. Furthermore, the signal from the substrate is significantly reduced during micro-Raman spectroscopy, resulting in a better signal-to-noise ratio. In addition, the silicon membranes are strong enough to support AFM and SEM characterization. As a result, these substrates provide a low cost, mass producible, efficient, and reliable platform for direct TEM, Raman, AFM, and SEM analysis of as-grown nanotubes or other nanomaterials on the same substrate, eliminating the need for any post-processing after CVD growth.

Gettering of Cu in Silicon Wafer by Using Cavitation Impacts

A novel gettering method using cavitation impacts is presented. Gettering is very important technique for IC manufacturing. Silicon wafers used as a substrate for semiconductors are often exposed to contamination during the device processes. If crystal defects are intentionally introduced into back-side of silicon wafer, metal impurities such as Cu and Fe in the wafer are trapped in the defects and gather into the region during heat cycles. As a result, the zone near the surface of the wafer that is used as active device region is kept off unwanted impurities. This technique is called gettering. In this paper, to introduce backside damage, which is one of the gettering techniques, cavitation impacts are utilized. Cavitation bubbles produce high-pressure impacts upon collapsing. The suitable damage can be introduced by controlling the intensity of cavitation impacts. The high speed submerged water jet with cavitation, i.e., a cavitating jet, was used to cause cavitation impacts. The cavitating jet can introduce backside damage without the use of particles, as in shot blasting that is popular technique. In order to confirm the gettering effectiveness of the damage introduced by a cavitating jet, an experimental study was carried out. The silicon wafer treated by the cavitating jet was intentionally contaminated with solution of Cu(NO3)2. The wafer was then thermally treated. The surface was observed after etching that makes defects on the surface observable. On the surface of the wafer having no gettering effectiveness, defects which were induced by contamination are observed. If the wafer has gettering effectiveness, defects are not observed on the surface. Gettering effectiveness of the damage introduced by the cavitating jet was shown.

Physical characteristics of the annealed/isolated-diamond film

Abstract The polycrystalline diamond films were deposited on the silicon substrate using a methane/hydrogen gas mixture in a microwave plasma-assisted chemical vapor deposition system. Prior to deposition, the silicon wafers were pretreated by a photoresist in which 0.1 μm powder is suspended. The isolated-diamond film was obtained by etching the backside of silicon wafer with KOH solution. From X-ray photoelectron spectroscopy analysis, the oxygenated phenomenon was detected for the as-deposited diamond film and increased for both surfaces of the isolated-diamond film after the back-etching process. A thick SiC (282.7 eV) and non-diamond components (285 eV) interface layer was found on the bottom surface of the isolated-diamond film. However, it was found that part of the interface layer (SiC and non-diamond components) was removed and the amorphous carbon (285.8 eV) was appeared for the bottom surface of the annealed/isolated-diamond film and the silicon signal was appeared for the top surface of the annealed/isolated-diamond film. It was also found that the oxygenated phenomenon increased considerably after the 800°C annealing process. However, from the Raman analysis, it was observed that the full width half maximum was changed from 5.0 to 4.6 cm−1 and from 6.0 to 5.4 cm−1 for the top and the bottom surfaces of the annealed/isolated-diamond film, respectively. It was concluded that the oxygenated phenomenon increased on both of the top and bottom surface layers of the annealed/isolated-diamond film. However, it was found that the oxygenated phenomenon did not degrade the film quality since the quality of the isolated-diamond film was improved after the high-temperature annealing process.

Characterization of Silicon Wafer Back Sides with Low Thermal Oxide Layers by Copper Deposition

Copper decoration was performed on silicon wafer back sides covered with a low thermal oxide (LTO) layer. Under the conditions applied, 50 V across the electrolytical cell for about 5 min, patches with a lateral extension of 150 μm and larger were generated, and can be observed visually with haze light illumination. The defects on the wafer back side causing decoration have characteristic lateral dimensions on the order of few micrometers, heights and depths of well below 1 μm up to several micrometers, and originate mostly from interactions of the silicon wafer back side with particles. In the case of silicon wafer back sides manufactured with intentional damage for external gettering and covered with a LTO, only such defects are clearly marked by copper decoration that deviate from the characteristic back side texture. Thus, copper decoration is a method that, for the first time, allows the systematic investigation of defects with micrometer dimensions on present standard commercially available and coated silicon wafer back sides. Location of the defects is accurate enough for high resolution characterization equipment such as atomic force microscopy or those that can be used for chemical analysis. © 2000 The Electrochemical Society. All rights reserved.

Excimer laser cleaning of silicon wafer backside metallic particles

An excimer laser cleaning system operating at 248 nm was developed to remove micrometer-sized metallic particles from the backside of silicon wafers. Deliberate iron contamination has been performed using iron-oxide particles having a diameter of 0.5–2 μm. The surface photovoltage (SPV) method was used to characterize the cleaning efficiency through the change in diffusion length and iron concentration in the silicon bulk. Following a rapid thermal annealing at 1050 °C for 4 min, the SPV measures diffusion lengths down to 40 μm for the iron-contaminated wafer, corresponding to an iron concentration up to 1.55×1013 cm−3. The minimum diffusion length increases to 130 μm after two steam laser cleanings done at a laser fluence below the silicon threshold damage of 200 mJ/cm2. The iron concentration measured in the bulk of the iron-contaminated wafers is reduced by more than 91%, to a concentration of 1.4×1012 cm−3.

Characterization of the Damage on the Back Side of Silicon Wafers

AbstractGettering represents a standard procedure to remove harmful impurities from device active regions of a silicon wafer. An affordable technique for the creation of a defect free (denuded) zone is the introduction of gettering sites on the wafer back side via mechanical damage (i.e. lapping). However, optimizing the extrinsic gettering process requires a technique to quantify the extent of damage introduced through a typical back-side damaging step. Here, we present results from a study using triple axis x-ray diffraction. We characterized the level of damage present in wafers subjected to different lapping conditions. By comparing reciprocal space maps from samples that had undergone different lapping steps, we concluded that all the as-lapped samples showed similar levels of damage in terms of both strain variations and lattice tilts. However, the integrated diffuse scattering intensities decreased from medium to soft t.-double-soft lapping, which confirmed that the double soft lapping introduced the least damage. Typically, the damage step introduced a symmetrical distribution of both lattice strain and lattice tilts (mosaicity) in the surface layer. KOH etching was employed to determine the depth of the damaged layer. In all cases the as-lapped samples had integrated intensities two orders of magnitude greater than those of the etched samples. Analysis of the residual damage present in the lapped samples after chemical etching confirmed that the more aggressive lapping conditions introduced damage of greater depth.

Substrate Doping and Microroughness Effects in RTP Temperature Measurement by In Situ Ellipsometry

The use of single‐wavelength ellipsometry for the measurement of the temperature of heavily doped and chemically roughened silicon wafers in a rapid‐thermal processing (RPT) environment was investigated. At an operating wavelength of 6328 Å, the measurement technique was found to be unaffected by either the substrate doping or surface microroughness of less than 500 Å. Similar results were obtained from room‐temperature measurements at other wavelengths. The roughness of the backside of silicon wafers exceeds 500 Å, and the ellipsometric parameter ψ was observed to decrease with increasing microroughness. Microroughness in excess of 500 Å introduced a systematic error in the temperature measured by ellipsometry that increased in magnitude with increasing surface microroughness. As a result, the unpolished surface of a wafer backside cannot be used to probe for temperature measurement.

Impurity Gettering in Silicon by Thin Polycrystalline Films

ABSTRACTCapability of impurity gettering by thin polycrystalline films on the backside of silicon wafer was evaluated by minority-carrier diffusion length. Cu was gettered easily during usual cooling after high temperature annealing. On the other hand, intentional slow cooling or low temperature annealing was necessary for effective Fe gettering. The gettering efficiency for Fe increased with lowering the annealing temperature when Fe was diffused sufficiently. From the quantitative consideration of Fe gettering, we propose the model of impurity gettering based on the chemical equilibrium of impurity reaction in polysilicon films. It was also expected that gettering efficiency increased with the thickness of polysilicon film.

Transfer of patterns from the backside of a silicon wafer coated with Si3N4 to its front surface during wet oxidation

Patterns on the backside of silicon wafers coated with Si3N4 films have been observed on their front surfaces after wet oxidation. This pattern transfer phenomenon is the result of a reduction in the oxidation rate of the front-surface nitride film over areas where the backside films have been removed. This reduction has been attributed to the influence of the stress in the nitride film on its oxidation rate. In areas where the backside nitride has been removed, localized sample bowing results in stress relief in the front-surface film and a lower oxidation rate of the nitride film.

Transmission electron microscopy of gold-silicon interactions on the backside of silicon wafers

Transmission electron microscopy of gold-silicon interactions on the backside of silicon wafers

Defect Generation and Gettering during Rapid Thermal Annealing

The generation of crystallographic defects induced by metallic impurities diffusing from the back side of silicon wafers is observed during rapid thermal annealing. The type of defect generated depends on both the type and concentration of metal used. Saucer‐pits, hillocks, and oxidation induced stacking faults are observed after oxidation in the time range 40–180s. These defects can be annihilated by gettering with a heavily doped P layer diffused into the back side of the wafers. The effectiveness of this annihilation depends upon the order of the gettering and defect‐generating processes. It also depends on the type and concentration of metal used.

Transmission electron microscopy of gold-silicon interactions on the backside of silicon wafers

The Au-Si interactions on the backside of 〈111〉 silicon wafers have been studied over the temperature range of 275–400 °C by transmission electron microscopy. The Au films annealed at temperatures below the Au-Si eutectic temperature (363 °C) all have similar structure—columnar Au grains of small size (∼450 Å). An orthorhombic gold silicide, Au3Si, forms at the Au/Si interface below the eutectic temperature due to the migration of Au into the silicon substrate. The Au3Si grains are of much larger size (∼2000 Å) than Au and contain twins. Annealing at 400 °C, which is above the eutectic temperature, results in a completely different structure. It consists of numerous small Si islands protruded and dispersed throughout a continuous, large grain (>2.8 μm), polycrystalline gold film. Gold silicide was not observed at 400 °C. Many Au grains are found to grow epitaxially on the silicon substrate. The silicon islands are also found to grow epitaxially on silicon substrate. The structure after 400 °C annealing is interpreted as the result of the eutectic reaction between the substrate Si and the overlaying Au film.