Characterization of Silicon Wafer Back Sides with Low Thermal Oxide Layers by Copper Deposition

Abstract

Copper decoration was performed on silicon wafer back sides covered with a low thermal oxide (LTO) layer. Under the conditions applied, 50 V across the electrolytical cell for about 5 min, patches with a lateral extension of 150 μm and larger were generated, and can be observed visually with haze light illumination. The defects on the wafer back side causing decoration have characteristic lateral dimensions on the order of few micrometers, heights and depths of well below 1 μm up to several micrometers, and originate mostly from interactions of the silicon wafer back side with particles. In the case of silicon wafer back sides manufactured with intentional damage for external gettering and covered with a LTO, only such defects are clearly marked by copper decoration that deviate from the characteristic back side texture. Thus, copper decoration is a method that, for the first time, allows the systematic investigation of defects with micrometer dimensions on present standard commercially available and coated silicon wafer back sides. Location of the defects is accurate enough for high resolution characterization equipment such as atomic force microscopy or those that can be used for chemical analysis. © 2000 The Electrochemical Society. All rights reserved.