Average Subthreshold Swing Research Articles

High drain field impact ionization transistors as ideal switches

Impact ionization effect has been demonstrated in transistors to enable sub-60 mV dec−1 subthreshold swing. However, traditionally, impact ionization in silicon devices requires a high operation voltage due to limited electrical field near the device drain, contradicting the low energy operation purpose. Here, we report a vertical subthreshold swing device composed of a graphene/silicon heterojunction drain and a silicon channel. This structure creates a low voltage avalanche impact ionization phenomenon and leads to steep switching of the silicon-based device. Experimental measurements reveal a small average subthreshold swing of 16 µV dec−1 over 6 decades of drain current and nearly hysteresis-free, and the operating voltage at which a vertical subthreshold swing occurs can be as low as 0.4 V at room temperature. Furthermore, a complementary silicon-based logic inverter is experimentally demonstrated to reach a voltage gain of 311 at a supply voltage of 2 V.

FS-iTFET: advancing tunnel FET technology with Schottky-inductive source and GAA design

In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal–semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (ION). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SSAVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SSAVG by 49% and achieves a superior ION/IOFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance

In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and high thermal budgets and streamlines the fabrication. The implementation of III–V compound material, i.e. low bandgap compound GaSb, in the source region, combined with the larger area gate normal line tunneling, improves the ON current for our proposed III–V JF L GNLTFET device. Additionally, the utilization of large bandgap GaAs compounds on the drain and channel sides eliminates ambipolarity and further enhances the performance of our proposed device. Meaning that the proposed device simultaneously improves the ON current and suppresses the ambipolarity. Our proposed III–V JF L GNLTFET exhibits enhanced output performance with an ON current of 23.2 μA μm−1 and a minimum and average subthreshold swing of 3.7 mV dec−1 and 15.82 mV dec−1 respectively. Furthermore, the proposed III–V JF L GNLTFET also gives superior RF/analog performance with transconductance (168.65 μS), cut-off frequency (33.52 GHz), gain-bandwidth product (5.11 GHz), and transconductance-frequency product (243.7 GHz).

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance

We introduce two novel III-V inverted T-channel vertical line tunnel field-effect transistor (TFET) configurations, leveraging staggered bandgap compound materials. Design D-1 operate s without negative capacitance, while Design D-2 incorporates negative capacitance. Both designs employ area-enhanced gate normal line tunneling with dual-gate impact, utilizing InGaAs and GaAsSb materials to effectively reduce the overall bandgap. The double-area line tunneling, facilitated by the double gate, significantly enhances performance. D-1 exhibits notable improvements, with an ION value reaching 596.55 μA/μm, an ION/IOFF ratio of 2.5 × 108, a minimum subthreshold swing (SS) of 9.75 mV/dec, and an average subthreshold swing (AVSS) of 31.93 mV/dec. Building upon these achievements, D-2 takes a step further by implementing NC through a ferroelectric layer gate stack, significantly increasing the line tunneling rate symmetrically on the left and right channels beneath both gates. This marks the first proposal of double gate area-enhanced line tunneling with negative capacitance in this paper. D-2 demonstrates remarkable performance for future low-power applications.

Noise analysis of NC-GAAFET cylindrical nanowire with non-uniform interface trap charge

In this article, low to high frequency noise behavior analysis of negative capacitance gate-all-around field effect transistor (NC-GAAFET) MFIS structure Silicon Nanowire (SiNW) device, using Sentauras TCAD simulations, is investigated. The NC-GAAFET SiNW yields on current (ION) 5.31 times larger and off current (IOFF) is significantly reduced by ∼ 105 orders compared to baseline SiNW. The device exhibits an excellent switching ratio of 5.2 × 1014. Average subthreshold swing for the NC-GAAFET is 33 mV/dec compared to 64 mV/dec of baseline nanowire. The Negative-DIBL for the device is −20 mV/V which outshines earlier findings. Furthermore, the drain current noise power spectral density (PSD) Sid, and input referred gate voltage noise PSD (Svg) are comprehensively analyzed in the presence of Gaussian trap (non-uniform) distribution. The analysis indicates that, flicker or (1/f) noise dominates in low frequency regime, generation-recombination (G-R) noise is more influential in mid frequency regime whereas in very high frequency regime diffusion noise is leading. The device exhibits least Sid(NET) and Svg(NET) at tfe = 6 nm compared to baseline, tfe = 5 nm, and 7 nm.

An InGaAs-based Fin-EHBTFET with a heterogate and barrier layer for high performance

This paper proposes a fin electron-hole bilayer tunneling FET with a heterogate and an InAlAs barrier layer (HBF-EHBTFET). The heterogate can suppress off-state leakage caused by point tunneling, while the InAlAs barrier layer prevents source–drain direct tunneling, significantly reducing the off-state current (I off). P-type Gaussian doping can not only solve the problem of the inability to generate a hole layer during device fabrication, but also reduce the turn-on voltage of line-tunneling, ultimately increasing on-state current and reducing average subthreshold swing (SS avg). By optimizing parameters of the heterogate and InAlAs barrier layer, HBF-EHBTFET can obtain I off of 2.37 × 10−16 A μm−1, SS avg of 17.97 mV dec−1, a cutoff frequency (f T) of 13.2 GHz, and a gain bandwidth product (GBW) of 1.58 GHz. Compared with traditional EHBTFET, HBF-EHBTFET exhibits a reduction in I off by four orders of magnitude, a decrease in SS avg by 65.27%, and an increase in f T and GBW by 78.59% and 93.62%, respectively.

Raised Ge-Source with n+ pocket and recessed drain line TFET: A proposal for biosensing applications

In this paper, we present a novel raised Ge-source with an n+ pocket and recessed drain line Tunnel Field-Effect Transistor (TFET). It offers enhanced performance for potential biosensing applications. The proposed device comprises a Ge source with a low bandgap, an n+ pocket, and a larger tunneling area. This results in improved performance characteristics: an ON current of 54.27 μA/μm, an ON-current to OFF-current ratio of 1.5 × 1012, and an average subthreshold swing of 21.3 mV/dec. The recessed drain design eliminates ambipolarity, further enhancing performance. The study thoroughly investigates biosensing capabilities, including DC and transient analyses, evaluating charged and neutral biomolecules (uricase, biotin, 3-aminopropyltriethoxysilane, DNA, keratin, and gelatin). The proposed biosensor, with a higher drain current sensitivity of 1.2 × 109 for gelatin (k = 12) and 3.05 × 108 for keratin (k = 8), outperforms existing approaches, making our proposed biosensor a compelling choice for future low-power biomedical applications.

Improvement of C-shaped pocket TFET with sandwiched drain for ambipolar performance and analog/RF performance

A novel structure of tunneling field effect transistor device (CSP-SD-TFET) is proposed, which adds a sandwiched drain to the C-shaped pocket TFET (CSP-TFET). This structure can increase the resistance of the drain, share the lateral electric field at the tunneling junction between the channel and the drain, reduce the lateral electric field at the tunneling junction, and suppress the generation of ambipolar current. The DC and analog/RF characteristics of CSP-SD-TFET are simulated and analyzed by Sentaurus TCAD, and the sandwiched structure parameters of the drain are optimized. The results show that the sandwiched drain structure suppresses the ambipolar current and on-state current, so the parameters of the sandwiched drain structure need to be a compromise between low ambipolar current and high on-state current. The optimized CSP-SD-TFET device has good DC characteristics, such as low average subthreshold swing SSavg (12.2mV/dec), high on/off current ratio Ion/Ioff (2.5 × 1011), high on-state current Ion (9.02 × 10−4 A/μm) and low ambipolar current Iamb (5.41 × 10−17A/μm). The RF performance of the CSP-SD-TFET, such as the cut-off frequency fT (1 × 1011 Hz) and gain-bandwidth product GBP (5.66 × 1010 Hz), are improved. It can be seen that the CSP-SD-TFET device not only has good DC characteristics but also improves analog/RF characteristics.

Steep slope threshold switching field‐effect transistors based on 2D heterostructure

AbstractIn dealing with the increasing power dissipation of electronic systems with increasing integration density, a field‐effect transistor (FET) with steep switching slope that overcomes the thermionic limit is vital to achieve low‐power operations. Here, we report two types of threshold switching (TS) FETs based on 2D Van der Waals heterostructures by virtue of the abrupt resistive switching of the hexagonal boron nitride (hBN) TS device. The common hBN dielectric layer functions as the switching medium for the TS device and the gate dielectric for the 2D FET enabling seamless integration of the hBN TS device and baseline 2D FET. TS FET in source configuration by connecting the TS device to the source terminal of the 2D FET offers an ultralow average subthreshold swing (SS) of 1.6 mV/dec over six decades of drain current at room temperature and suppressed leakage current. TS FET in gate configuration by connecting the TS device to the gate terminal of the 2D FET also exhibits steep switching slope with ultralow SS of 10.6 mV/dec. The proposed compact device structures integrating 2D FET and TS device provide a potential approach of monolithic integration toward next‐generation low‐power electronics.

Overcoming the Unfavorable Effects of "Boltzmann Tyranny:" Ultra-Low Subthreshold Swing in Organic Phototransistors via One-Transistor-One-Memristor Architecture.

Organic phototransistors (OPTs), as photosensitive organic field-effect transistors (OFETs), have gained significant attention due to their pivotal roles in imaging, optical communication, and night vision. However, their performance is fundamentally limited by the Boltzmann distribution of charge carriers, which constrains the average subthreshold swing (SSave ) to a minimum of 60mV/decade at room temperature. In this study, an innovative one-transistor-one-memristor (1T1R) architecture is proposed to overcome the Boltzmann limit in conventional OFETs. By replacing the source electrode in an OFET with a memristor, the 1T1R device exploits the memristor's sharp resistance state transitions to achieve an ultra-low SSave of 18mV/decade. Consequently, the 1T1R devices demonstrate remarkable sensitivity to photo illumination, with a high specific detectivity of 3.9 × 109 cm W-1 Hz1/2 , outperforming conventional OPTs (4.9 × 104 cm W-1 Hz1/2 ) by more than four orders of magnitude. The 1T1R architecture presents a potentially universal solution for overcoming the detrimental effects of "Boltzmann tyranny," setting the stage for the development of ultra-low SSave devices in various optoelectronic applications.

Performance investigation of elevated source EBG TFET based photosensor for near-infrared light sensing applications

In this manuscript, an elevated source TFET with extended back gate (ES-EBG-TFET) based photosensor is designed to offer improvement in optical performance for detecting incident light of narrow-spaced wavelengths (∼100 nm) and low luminous intensity (<0.9 W/cm2) in the near-infrared (IR) range. The proposed photosensor combines the advantages provided by both the elevated top gate and extended back gate in the sense of increasing the line tunneling region at the source-channel (S–C) interface, resulting to improvement in illumination current (ILight), threshold voltage (Vth) and average subthreshold swing (SSavg) under the light state. Furthermore, the inclusion of an L-shaped pocket around the source region helps to reduce the corner effects at S–C interface in the sub-threshold region, thereby improving the signal-to-noise ratio (SNR) of the proposed photosensor for on-chip applications. Due to improved optical generation in the photosensing gate, a high spectral sensitivity (Sn) of ∼54 is achieved for ES-EBG-TFET based photosensor because the variation in wavelength (λ) of incident light from 1050 to 750 nm shows a two order change in ILight (ID at Vgs = 0.2V under light state) from 3.1 × 10−15 A/μm to 1.72 × 10−13 A/μm, respectively. Since the elevated source provides a space to create larger illumination window above the channel region, a high optical generation rate is observed for the proposed photosensor under the incident light with low intensity (<0.9 W/cm2). The maximum value of SNR is observed to be 66.4 dB at a λ of 750 nm, while the quantum efficiency (ƞ) and responsivity (R) are reported to be 74% and 0.59 A/W, respectively, around λ of 1050 nm. Moreover, an optimum length of back-gate underlap with drain (LBGUD) is found to enhance the magnitude of SNR (at λ of 750 nm) and Sn (750–1050 nm) from 25.6 to 63.1 dB and 14 to 52.8, respectively when the photosensor is operated at the ambipolar state (Vgs = −0.6 V and Vds = 0.5 V). Finally, the photosensing parameters such as Sn and SNR are analyzed under the presence of acceptor and donor interface traps and it is found that there is insignificant degradation in the optical performance of the proposed photosensor.

Physics based analysis of a high-performance dual line tunneling TFET with reduced corner effects

To improve the DC and analog/HF performance, a novel dual line tunneling based TFET (DLT-ES-TFET) with elevated source and L-shaped pocket is proposed in this manuscript. In DLT-ES-TFET, the elevated top (G1) and extended back (G2) gates overlapping the source region enhance the line tunneling of charge carriers in both vertical and horizontal directions across the source-pocket interface. TCAD-based simulation results reveal that DLT-ES-TFET offers an improvement of ∼47% and ∼54% in average subthreshold swing when it is compared with E-VTSFET and L-TFET, respectively. Furthermore, ON-current in DLT-ES-TFET is also found to be improved by an order of ∼1 as compared to other two devices. In fact, the L-shaped pocket reduces the corner effects caused by the electric filed crowding across source-channel (S-C) interface, which eventually suppresses the OFF-state leakage in the proposed DLT-ES-TFET. Moreover, enhancement in the charge carriers tunneling across S-C interface leads to a huge increment in the transconductance (∼157μs/μm) of DLT-ES-TFET, which further helps in achieving a high cut-off frequency of 12.3 GHz. Next, transient response of DLT-ES-TFET-based resistive load inverter suggests a notable improvement in peak over- and under-shoots along with propagation delay as compared to E-VTSFET and L-TFET. Lastly, interface traps and temperature analysis is also found to be in favor of the proposed DLT-ES-TFET.

Ultrafast Negative Capacitance Transition for 2D Ferroelectric MoS2/Graphene Transistor.

Negative capacitance gives rise to subthreshold swing (SS) below the fundamental limit by efficient modulation of surface potential in transistors. While negative-capacitance transition is reported in polycrystalline Pb(Zr0.2Ti0.8)O3 (PZT) and HfZrO2 (HZO) thin-films in few microseconds timescale, low SS is not persistent over a wide range of drain current when used instead of conventional dielectrics. In this work, the clear nano-second negative transition states in 2D single-crystal CuInP2S6 (CIPS) flakes have been demonstrated by an alternative fast-transient measurement technique. Further, integrating this ultrafast NC transition with the localized density of states of Dirac contacts and controlled charge transfer in the CIPS/channel (MoS2/graphene) a state-of-the-art device architecture, negative capacitance Dirac source drain field effect transistor (FET) is introduced. This yields an ultralow SS of 4.8mV dec-1 with an average sub-10 SS across five decades with on-off ratio exceeding 107, by simultaneous improvement of transport and body factors in monolayer MoS2-based FET, outperforming all previous reports. This approach could pave the way to achieve ultralow-SS FETs for future high-speed and low-power electronics.

A new approach for ammonia gas sensing using a source pocket dopingless tunnel FET with PANI catalyst

This article presents a new ammonia (NH3) gas sensor designed using a dopingless tunnel field effect transistor with a SiGe source pocket (SP-DLT) and investigates its sensitivity using a polyaniline (PANI) conducting polymer as the gate catalyst. PANI nanofiber has a greater specific surface area and a linked network structure, which increases its sensing performance as a catalyst. Combining an HfO2 gate dielectric and SiGe source pocket improves the drain current. The sensing film is deprotonated when the PANI conducting polymer is exposed to the gas, reducing the film’s resistance. As a result, more electron or proton transfer is possible, ensuring a more substantial interaction between the sensor and the analyte gas. This modulates the electrical characteristics and work function of the TFET. The sensor’s electrical performance is examined in terms of drain current, average subthreshold swing (SS), electric field, band-to-band tunneling rate (BTBT), and energy band diagram for an ammonia gas pressure (AGP) range of 10−12 torr to 10−9 torr. The sensitivity and selectivity of the proposed PANI-SP-DLT sensor in terms of different metrics, including drain current, average SS, current ratio, transconductance, and gain factor, are further investigated. The study is expanded to consider the impact of temperature affectability and the germanium mole fraction on current sensitivity performance. The Silvaco ATLAS device simulator is used for the brief simulation work for the developed gas sensor.

A High-Performance InGaAs Vertical Electron-Hole Bilayer Tunnel Field Effect Transistor with P+-Pocket and InAlAs-Block.

To give consideration to both chip density and device performance, an In0.53Ga0.47As vertical electron-hole bilayer tunnel field effect transistor (EHBTFET) with a P+-pocket and an In0.52Al0.48As-block (VPB-EHBTFET) is introduced and systematically studied by TCAD simulation. The introduction of the P+-pocket can reduce the line tunneling distance, thereby enhancing the on-state current. This can also effectively address the challenge of forming a hole inversion layer in an undoped InGaAs channel during device fabrication. Moreover, the point tunneling can be significantly suppressed by the In0.52Al0.48As-block, resulting in a substantial decrease in the off-state current. By optimizing the width and doping concentration of the P+-pocket as well as the length and width of the In0.52Al0.48As-block, VPB-EHBTFET can obtain an off-state current of 1.83 × 10-19 A/μm, on-state current of 1.04 × 10-4 A/μm, and an average subthreshold swing of 5.5 mV/dec. Compared with traditional InGaAs vertical EHBTFET, the proposed VPB-EHBTFET has a three orders of magnitude decrease in the off-state current, about six times increase in the on-state current, 81.8% reduction in the average subthreshold swing, and stronger inhibitory ability on the drain-induced barrier-lowering effect (7.5 mV/V); these benefits enhance the practical application of EHBTFETs.

Inkjet‐Printed, Wafer‐Scale Organic Schottky‐Gate Transistors toward Single‐Battery‐Driven Integrated Logic

AbstractOrganic field‐effect transistors switched by insulated gates are the most essential building blocks, while usually plagued with degraded gate control arising from complicated dielectric engineering. Subsequently, the resulting large supply voltage and power consumption remain an essential issue for portable electronics driven by a single battery of only 1.5 V. Herein, wafer‐scale organic Schottky‐gate transistor arrays using inkjet‐printed few‐layer organic semiconducting crystals are reported. The transistors exhibit steep switching characteristics with an average subthreshold swing of 55 mV per dec and high signal amplification efficiency over 45 S A‐1, attributed to efficient Schottky gating and enhanced charge injection. Thereafter, high‐gain inverters are successfully demonstrated with an ultralow power consumption of only 800 pW; also, they are integrated as 1 V driven sequential logic circuits. A coplanar double‐gate geometry is also introduced for low‐voltage, single‐device AND logic. Therefore, the work opens new avenues toward the sustainable advancement in single‐battery‐driven, ultralow‐power organic electronics.

Enhancing subthreshold slope and ON-current in a simple iTFET with overlapping gate on source-contact, drain Schottky contact, and intrinsic SiGe-pocket

In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high ION current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the ION current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.Savg = 16.2 mV/Dec and S.Smin = 4.62 mV/Dec, respectively. At VD = 0.2 V, the ION current is 1.81 times 10–6 A/μm, and the ION/IOFF ratio is 1.34 times 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

Ultra‐Steep‐Slope and High‐Stability of CuInP2S6/WS2 Ferroelectric Negative Capacitor Transistors by Passivation Effect and Dual‐Gate Modulation

AbstractFerroelectric negative capacitance transistors (Fe‐NCFETs) have emerged as a promising technology for low‐power electronics and have the potential to continue Moore's law. However, the existing 2D ferroelectric materials are predominantly sulfides or halides, which are susceptible to oxidation or hydrolysis, thereby hindering their commercial production due to concerns related to performance and stability. To address these obstacles, the authors have optimized the Fe‐NCFETs composed of 2D ferroelectric CuInP2S6 and semiconductor WS2 using high‐k Al2O3 passivation and dual‐gate modulation strategy. With atomic layer deposition (ALD) of Al2O3, all‐2D Fe‐NCFETs, operated at a low driven voltage of 0.3 V, achieve much improvement in stability and performance with a high ON/OFF ratio of 109 and minimum subthreshold swing (SS) of 14 mV dec−1, which is attributed to the negative capacitance effect of CuInP2S6 and passivation effect of ALD‐Al2O3. The dual‐gate modulation approach is also implemented to maintain the device stability and enable the improved ON/OFF ratio from 105 to 108, minimum SS of 10 mV dec−1, and an average SS of ≈60 mV dec−1 covering more than five orders of magnitude of current. This work provides a facile and effective strategy for designing all‐2D Fe‐NCFETs with ultra‐steep SS and high stability, showing exciting potential for future low‐power electronic applications.