Abstract Power consumed by the CUT (Circuit Under Test) during testing is a major concern in the design of DFT. Power lost due switching activity is the major part of the power dissipated in technology node higher than 45nm. When the Chip is in Functional mode there is some switching power dissipated in the scan-chains. Similar switching power dissipation is observed in the logical clouds also when the Chip is in test mode. The authors propose a novel design of Scan-Cell to reduce power dissipation. The design is implemented in UM CMOS 0.18µm technology. The simulations are carried for two RC-Corners (slow max and fast min). 10.80% reduction in average power dissipation is observed in scan mode and 18.37% reduction in average power dissipation is observed in functional mode. 40.00% increase in the area is observed for each scan-cell. 17.3813% increase in the total area of the design is observed after replacing the SDFFs with PSDFF.