Average Power Dissipation Research Articles

A baseband codec for digital cellular telephony

The authors describe the design of a baseband codec for European and North American digital cellular telephone applications. By integrating all the data conversion circuitry, this chip offers a low-cost, low-power solution to baseband signal processing and control functions. The receive section has two paths to process the in-phase and quadrature-phase components of the signal. Each path consists of a programmable gain amplifier (PGA) and a 10-b sigma-delta analog/digital (A/D) converter. Two 8-b digital/analog (D/A) converters generate the in-phase and quadrature-phase components of the transmit signal. A 9-b digital-analog converter (DAC) and a 10-b DAC are provided to perform auxiliary control functions. The chip is fabricated using a 0.9- mu m CMOS technology and has an area of 21 mm/sup 2/. The average power dissipation is 85 mW. >

Magnetospheric interaction with Triton's ionosphere

The large electron densities measured by the Voyager radio occultation experiment are attributed to the precipitation of magnetospheric electrons with energy > 10 keV. Because the ionospheric electric Pedersen conductivity of Triton is,∼ (1−2) × 104 mho and the Alfven conductance is ∼ 3.5 mho, direct connective flow of plasma into the essentially infinitely conducting ionosphere is negligible. Magnetospheric electrons are transported to Triton's ionopause by curvature drift as a result of weak magnetic field line draping in a sub‐Alfvenic plasma interaction with Triton. At the ionopause energetic electrons have a high probability of elastic and inelastic scattering and precipitate into the upper atmosphere. The average power dissipation is estimated to be ∼ (2−3) × 108 W.

An enhanced technique for simulating short-circuit power dissipation

A circuit-simulation technique which permits the measurement of the average short-circuit power dissipation component in integrated circuits using SPICE is presented. It is an extension of a previously presented scheme by S.M. King (see ibid., vol.21, no.5, p.889-91, 1986) which measures average power dissipation while circuits are being simulated. The extended technique is most appropriate for low-power circuit design. It can be applied effectively to any complementary circuit structure, such as CMOS, that does not permit current flow (other than leakage current) during steady-state operation. Results for differently W/sub p//W/sub n/ ratioed W/sub p//W/sub n/ CMOS circuits are shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fabrication, RE performance, and yield of a combined limiting amplifier and dual-modulus prescalar GaAs IC chip

Production technology details, RF performance, and yield results for an ECL-compatible, L-band, limiting dual-modulus (/10/11) prescalar are presented. Monolithic integration of analog and digital circuit functions is achieved using refractory self-aligned-gate FET technology. When tested with -22-dBm input signal power, one lot of six wafers had a total RF chip yield of 19% with a best-wafer yield of 43%. The average operating frequency was 1.45 GHz (SD=51 MHz) with an average power dissipation of 696 mW (SD=23 mW).< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An enhanced power meter for SPICE2 circuit simulation

An enhancement to a technique presented by S.M. Kang (IEE J. Solid-State Circuits, vol.SC-21, p.889-91, Oct. 1986) for measuring average power dissipation during a SPICE circuit simulation is described. A modified power meter circuit is discussed that allows power measurement during an arbitrary interval of time, holds a constant final value at the end of the sampling interval, and improves the resolution of the technique. Simulation results comparing the modified power meter with the original power meter are presented to verify the modification. An optional modification to provide for a variable power supply voltage is also included. >

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.

Performance of carry lookahead generator circuit fabricated with gallium arsenide

A high-performance 4-bit carry lookahead generator macrocell integrated circuit similar to the commercial 2902, a member of the 2900-family microprocessor chip set, was designed and built using direct-coupled FET logic (DCFL) and buffered FET logic (BFL) GaAs technologies. The following propagation delay times and power dissipations were measured: DCFL version -T/SUB pd/=1.55 ns, P=34 mW; BFL version-T/SUB pd/=1.10 ns, P=520 mW. In contrast, the commercially available bipolar 2902 has a propagation delay (room temperature typical) of 4.5 ns with an average power dissipation of 260 mW.

Design and application of a 2500-gate bipolar macrocell array

A very high-speed 2500-gate Si bipolar macrocell array has been developed using a novel macrocell design approach and a 1-/spl mu/m rule advanced super self-aligned process technology (SST-1A). Using this macrocell array, a 16-bit parallel multiplier is designed and fabricated. The sophisticated circuit design of the macrocell array approach permits this complex function, which is equivalent to having 3024 NOR gates, using only 70% of the total of 756 internal cells. Consequently, a fast multiplication time of 7.5 ns is achieved with a 2.07-W power dissipation. Excellent performance with an average gate delay of 120 ps and average power dissipation of 0.365 mW is demonstrated for an equivalent NOR gate.

Low power microwave bubble generator

In this paper we discuss experimental results, dwelling particularly on the frequency sensitivity of the minimum microwave field necessary for bubble generation. A broad-band coplanar waveguide circuit was developed to provide leveled microwave power to a 4 μm by 4 μm shorting region producing highly local and intense microwave magnetic fields. In the samples employed, extremely low microwave fields generate bubbles, implying power dissipation in the μW range. We feel that when the system is scaled up to the large anisotropy field values of conventional magnetic bubble devices, the power dissipation will increase dramatically. However, our experimentation has revealed that microwave pulses shorter than 25 nsec may be used to generate bubbles. Due to the anticipated low average power dissipation, such a device may have an advantage over conventional bubble generators.

An LSI technology fully compatible EAROM cell : Guido Torelli. Alta Freq., LI (6), 345 (November–December 1982)

The design of a mixed mode 64-channel ASIC for digital readout of silicon strip detectors used in X-ray imaging applications is presented. The design is implemented in a 0.8 μm CMOS n-well epi-type substrate technology. The single channel consists of a charge sensitive preamplifier, a shaping amplifier, a discriminator and a pseudo-random 20-bit counter. In addition to the 64-channel core which is responsible for signal processing and data storage, the IC comprises additional blocks like an internal calibration circuit, internal DACs and a command decoder which governs communication of the IC with the external world. Those blocks have been designed keeping in mind testability features and using the chips for building multi-chip modules. The equivalent input noise charge measured at room temperature for a detector capacitance of 2.5 pF and signal integration time of 0.7 μs is 167 e− rms. The average power dissipation is 2.5 mW/channel. The channel-to-channel offset spread referred to the input is only 28 e− rms, while the standard deviation of gain spread is 0.5% of the mean value. The chip occupies area of 2.8×6.5 mm2.

Direct-coupled high speed adder by using Josephson junction

This paper presents the latest design work of high speed adder logic based on Josephson elements. The Josephson adder uses a novel exclusive-OR logic and performs high speed carry propagation technique. The idea of directionality is also undertaken to avoid the necessary distortion in carry signal. The principle of operation with salient feature of simulation of the adder are presented in full detail. Necessary checks for carry skip and other fabrication parameters are investigated using detailed model of the device based on its highly miniaturized size. The results of the simulation show that the nominal delay of the adder logic is 20 ps/stage and average power dissipation is 47 μW/stage. Authors have mainly stressed upon how to obtain ultra fast speed at the cost of very low power dissipation of the presented adder with its small size.

Current accessed magnetic bubble devices: Projections of performance

A critical analysis is made of the current accessed dual conductor perforated sheet magnetic bubble devices introduced by Bobeck, et al. First, the performance of the existing reported devices is considered. It is shown that although the average power dissipation to propagate one bit of data is relatively high, that with proper chip organization, the average on-chip power dissipation can be kept to tolerably low levels. However, certain components such as the nucleator and the bubble stretcher have such high power dissipation that they are expected to lead to local power dissipation problems on the chip. Assuming these local power dissipation problems can be solved, an analysis of the performance shows that these new devices potentially offer substantially higher data rates and substantially shorter access time than can be obtained with field accessed devices. Scaling rules are developed for the various components on current accessed devices. These scaling rules indicate that for most components, power dissipation per unit area will increase in inverse proportion to the circuit period. Power dissipation in the stretcher, on the other hand, increases even more rapidly with decreasing period and in a 1 Mbit device with 4 μm period would consume 80 percent of the on-chip power. Assuming the problems with power dissipation per unit area can be solved, the scaling rules suggest that the current accessed devices will enjoy an increasing performance advantage over field accessed devices as circuit period is reduced and the chip capacity is increased. This is because the data rate of current accessed devices is projected to increase in inverse proportion to circuit period, whereas the data rate of field accessed devices is dependent on the rotating field drivers and expected to remain constant.

A High Performance I2L Compatible with Subnanosecond ECL Devices

This paper describes a new approach for realizing a high performance I2L and a subnanosecond ECL circuit simultaneously on a single chip. Significant features of such a technology are a buried base structure for I2L gate and an implanted self-aligned contact (ISAC) structure for ECL circuit combined with dielectric isolation technology. The contributions of device parameters to the I2L characteristics are analyzed to get high speed operation. Following typical data of these advanced structures on a same chip are obtained with optimizing process parameters for a 4 µm design rule; (1) a maximum toggle frequency of I2L flip-flop circuit is 95 MHz with an average power dissipation of 185 µW/gate, (2) a power-delay product of I2L gate is 45 fJ for the fan-out of 3 at injector current of 1 µA/gate, and (3) ECL gate delay time of 0.68 nsec is obtained with switching current of 0.46 mA on a same chip.

Design of 2.5-Micrometer Josephson Current Injection Logic (CIL)

This paper describes Josephson Current Injection Logic (CIL) circuits. The design of the basic logic circuits, the two-and four-input OR and AND gates, and a timed inverter circuit, is presented in full detail and the logic delay and its sensitivity to design and fabrication parameters are investigated using detailed models of devices based on a 2.5-µm technology. The nominal logic delay of the circuits is estimated at 36 ps per gate for an average fan-in of 4.5 and fan-out of 3. The corresponding average power dissipation is 3.4 microwatts per gate. Finally, experimental delay measurements are presented for two-input and four-input OR and AND gates. The delay experiments are in excellent agreement with computer simulations.

A 30-ps Josephson current injection logic (CIL)

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.

Delay measurement of experimental 2.5-μm Josephson current injection logic (CIL)

Switching speeds of experimental Josephson interferometer circuits are measured on chains of current injection logic (CIL) gates fabricated using 2.5-μm minimum features. Logic delay of 32 ps per gate is measured for a four-input OR gate with a fan-out of 2. The average power dissipation of the four-input OR gate is 4 μW and the corresponding power-delay product is 1.28×10−16 J. For four-input AND gates the measured logic delay is 60 ps, the power dissipation is 6 μW, and the power-delay product is 3.6×10−16 J. The results are found to be in excellent agreement with estimates based on computer simulations.

Stochastic stability of an L-R circuit with a randomly fluctuating resistance

The statistical characteristics of a simple electrical circuit consisting of an inductance and a randomly fluctuating resistance excited by a randomly fluctuating voltage are investigated. The resistance is assumed to consist of both a deterministic and a stochastic part. The stability of the average current and autocorrelation function of the current is discussed. The instantaneous average power dissipation across the resistance and its asymptotic behaviour are also computed.

128-bit multicomparator

A 128-bit multicomparator was designed to perform the search-sort function on arbitrary length data strings. Devices can be cascaded for longer block lengths or paralleled for bit-parallel, word-serial applications. The circuit utilizes a 3-phase static-dynamic shift register cell for data handling and a unique gated EXCLUSIVE-NOR circuit to accomplish the compare function. The compare operation is performed bit parallel between a `data' register and a `key' register with a third `mask' register containing DON'T CARE bits that disable the comparator. The multicomparator was fabricated using p-channel silicon-gate metal-oxide-semiconductor (MOS) technology on a 107/spl times/150 mil chip containing 3350 devices. With transistor-transistor logic (TTL) input, data rates in excess of 2 MHz have been attained. The average power dissipation was 250 mW in the dynamic mode and 300 mW in the static mode.

A 64-kbit block addressed charge-coupled memory

This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil2and the total chip size is 218 × 235 mil2. The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.

An experimental multiplier circuit based on superconducting Josephson devices

This paper describes the design, testing, and operation of a 4-bit multiplier circuit based on Josephson tunneling logic (JTL) gates. The algorithm adopted was that of a simple serial 4-bit multiplier consisting of a 4-bit adder with ripple carry, together with a four phase, 8-bit accumulator shift register. The circuit, fabricated using a 25-/spl mu/m minimum linewidth technology, operated with a minimum cycle time of 6.67 ns (a limit imposed by the external test equipment) giving a 4-bit multiplication time of 27 ns with an average power dissipation of 35 /spl mu/W per logic gate. With better external pulse generators, or internal Josephson junction generators, the present circuit has been simulated to operate with a 3.0-ns cycle giving a 4-bit multiplication time of 12 ns.