Abstract
This paper describes a new approach for realizing a high performance I2L and a subnanosecond ECL circuit simultaneously on a single chip. Significant features of such a technology are a buried base structure for I2L gate and an implanted self-aligned contact (ISAC) structure for ECL circuit combined with dielectric isolation technology. The contributions of device parameters to the I2L characteristics are analyzed to get high speed operation. Following typical data of these advanced structures on a same chip are obtained with optimizing process parameters for a 4 µm design rule; (1) a maximum toggle frequency of I2L flip-flop circuit is 95 MHz with an average power dissipation of 185 µW/gate, (2) a power-delay product of I2L gate is 45 fJ for the fan-out of 3 at injector current of 1 µA/gate, and (3) ECL gate delay time of 0.68 nsec is obtained with switching current of 0.46 mA on a same chip.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
