Automatic Gain Control Loop Research Articles

Design of a ±0.15 dB accurate baseband detector for FMCW radars employing inherent PVT cancellation

This study presents design methodologies for high accuracy baseband detectors for use in automatic gain control (AGC) loops. These loops are used in many applications to stabilise the signal level in a transceiver chain. In a wireless frequency modulated continuous wave (FMCW) radar receiver for example, it is desired to maintain a constant baseband signal level at the receiver output prior to the analogue-to-digital converter. Due to the AGC loop feedback action, the accuracy of this output level directly depends on the detector accuracy. In this study, a detector design employing inherent cancellation of process, voltage and temperature (PVT) variations without the need for any complex compensation schemes is proposed. Measurement results of a fabricated test chip are in good agreement with simulations achieving ±0.15 dB accuracy over temperature, supply and part-to-part variations. The fabricated detector prototype on an IBM 0.18 µm technology has an active area of 0.05 mm2 and draws 1 mA from a 3 V supply. An integrated AGC loop including the proposed detector achieves a 52 dB dynamic range consuming an overall 9 mW power. To the best of the authors’ knowledge, the proposed detector has the highest uncalibrated accuracy reported up to date.

A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single <italic>LC</italic> VCO in 90 nm CMOS

A dual-lane DC-to-12.5 Gb/s all-rate clock and data recovery (CDR) IC with a single LC voltage-controlled oscillator is fabricated in a 90 nm CMOS. An all-rate clock divider with an asynchronous phase calibration scheme is employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme that adjusts the bandwidth of a CDR in the background for optimal bit error rate (BER) performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR consumes 244 mW at 12.5 Gb/s under dual-lane operation with an input sensitivity of 12 mVpp,diff. The CDR supports referenceless allrate operation with a BER <; 10 -12 on PRBS31 and compensates for 20 dB of channel loss using a continuous-time linear equalizer (CTLE), a one-tap decision feedback equalizer (DFE), and a three-tap pre-emphasis filter. The power efficiency of the test chip is 9.76 mW/Gb/s.

A novel oscillation control for MEMS vibratory gyroscopes using a modified electromechanical amplitude modulation technique

This paper reports a novel oscillation control algorithm for MEMS vibratory gyroscopes using a modified electromechanical amplitude modulation (MEAM) technique, which enhances the robustness against the frequency variation of the driving mode, compared to the conventional EAM (CEAM) scheme. In this approach, the carrier voltage exerted on the proof mass is frequency-modulated by the drive resonant frequency. Accordingly, the pick-up signal from the interface circuit involves a constant-frequency component that contains the amplitude and phase information of the vibration displacement. In other words, this informational detection signal is independent of the mechanical resonant frequency, which varies due to different batches, imprecise micro-fabrication and changing environmental temperature. In this paper, the automatic gain control loop together with the phase-locked loop are simultaneously analyzed using the averaging method and Routh–Hurwitz criterion, deriving the stability condition and the parameter optimization rules of the transient response. Then, a simulation model based on the real system is set up to evaluate the control algorithm. Further, the proposed MEAM method is tested using a field-programmable-gate-array based digital platform on a capacitive vibratory gyroscope. By optimizing the control parameters, the transient response of the drive amplitude reveals a settling time of 45.2 ms without overshoot, according well with the theoretical prediction and simulation results. The first measurement results show that the amplitude variance of the drive displacement is 12 ppm in an hour while the phase standard deviation is as low as 0.0004°. The mode-split gyroscope operating under atmospheric pressure demonstrates an outstanding performance. By virtue of the proposed MEAM method, the bias instability and angle random walk are measured to be 0.9° h−1 (improved by 2.4 times compared to the CEAM method) and 0.068° (√h)−1 (improved by 1.4 times), respectively.

Loop gain stabilizing with an all-digital automatic-gain-control method for high-precision fiber-optic gyroscope.

For a fiber-optic gyroscope (FOG) using electronic dithers to suppress the dead zone, without a fixed loop gain, the deterministic compensation for the dither signals in the control loop of the FOG cannot remain accurate, resulting in the dither residuals in the FOG rotation rate output and the navigation errors in the inertial navigation system. An all-digital automatic-gain-control method for stabilizing the loop gain of the FOG is proposed. By using a perturbation square wave to measure the loop gain of the FOG and adding an automatic gain control loop in the conventional control loop of the FOG, we successfully obtain the actual loop gain and make the loop gain converge to the reference value. The experimental results show that in the case of 20% variation in the loop gain, the dither residuals are successfully eliminated and the standard deviation of the FOG sampling outputs is decreased from 2.00 deg/h to 0.62 deg/h (sampling period 2.5 ms, 10 points smoothing). With this method, the loop gain of the FOG can be stabilized over the operation temperature range and in the long-time application, which provides a solid foundation for the engineering applications of the high-precision FOG.

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques

This paper presents a digital bang–bang phase-locked loop (DBPLL) that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. Due to noise filtering properties, a DBPLL has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the automatic loop gain control technique, the DBPLL can automatically attain this loop gain in background to minimize the jitter. This paper also exploits time-series analysis to analyze the DBPLL. In particular, the closed-form gain of a bang–bang phase detector (BBPD) is first derived, taking into account reference clock noise and oscillator noise simultaneously. The chip was fabricated in a 40 nm CMOS process. This DBPLL achieves $ fs integrated rms jitter and $ dBc reference spurs. It consumes 3.8 mW from a 1.1 V supply while operating at 3.96 GHz. This translates to an figure-of-merit (FOM) of $- 245$ dB.

An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs

An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 $\mu$ m $\times$ 170 $\mu$ m.

Digital Control System for the MEMS Tuning Fork Gyroscope Based on Synchronous Integral Demodulator

This paper presents a demodulation algorithm based on the synchronous integrator circuit for the MEMS tuning fork gyroscope utilizing the digital processing technology. The synchronous integral demodulator (SID) is adopted to demodulate the drive-detection signal and sense-axis output signal separately. Combining with automatic gain control and phase-locked loop technology, the closed-loop control of drive mode has been implemented, and high precision output of the gyroscope has been achieved. The simulation results have verified the effectiveness of the synchronous integrator circuit, which is in good agreement with the theoretical analysis. Compared with other demodulation algorithms, the SID has the advantages of the lower noise level, a better ability to attenuate the harmonics, and the best hardware efficiency. The frequency characteristic of the synchronous integrator is also analyzed, which is vital to the bandwidth of gyroscope. The print circuit board based on field-programmable gate array digital circuit is manufactured and the corresponding experiment is carried out. The experimental results show that the SID algorithm of digital control system for the gyroscope developed in our laboratory has achieved a good performance. The bias instability of tested gyroscope is measured to be 0.2°/h with the angle random walk of 0.14°/ $\surd \text{h}$ and the nonlinearity of the scale factor is <60 ppm with the measurement range of ±100°/s.

A low-power ADC with compact AGC loop for LR-WPAN receivers

This paper presents a novel pipelined analog-to-digital converter (ADC) with a dB-linearity automatic gain control (AGC) loop that exhibits both power and area efficiencies for low-rate wireless personal area network (LR-WPAN) receiver applications. The AGC loop is designed based on feedback architecture for high linearity and a full-digitally control method is proposed to simplify the gain adjusting. The sample-and-hold amplifier less (SHA-less) scheme is employing in ADC design, and moreover, an evaluation-time-sharing technique which combined opamp- and capacitor-sharing is presented for low power consumption and elimination of memory effect. The proposed circuit shows a gain error less than ±0.56 dB in a wide dynamic range of about 70 dB by 2 dB/step and achieves a maximum IIP3, SNDR, SFDR of 16.27 dBm, 41.87 dB, 58.72 dB, respectively. Designed in a 0.18 μm CMOS technology, the proposed circuit has been integrated in the LR-WPAN transceiver. The chip area is as small as 0.94 mm2 and the total power consumption is only 7.62 mW from a 1.8 V single supply.

Waveform Aliasing in Satellite Radar Altimetry

The full deramp pulse compression scheme employed by satellite radar altimeters digitizes each radar echo at a sampling rate matched to the chirp bandwidth. Echo power is undersampled by a factor of 2 when the power samples are simply obtained by squaring the magnitude of the echo samples, without first resampling, as is done in all altimeters to date. This results in inadequate sampling of the leading edge of the waveform if the significant wave height (SWH) is low. For a typical Ku-band altimeter with a chirp bandwidth of 320 MHz, simple squaring should be inadequate over ocean surfaces with SWH less than 2 m, that is, half of the ocean. Simply zero-padding the digital samples prior to range Fourier transform alleviates the problem introduced by magnitude squaring. Data from the CryoSat altimeter are used to demonstrate this remedy, and it is found that this reduces the variance in estimated range by 10% and in SWH by 20%. These improvements are confined to a range of SWH values between 1 and 4 m. Zero-padding also seems to have some small impact on values estimated over very flat surfaces (SWH ≪ 1 m), although theory suggests that better resolution of such surfaces would require a bandwidth exceeding 320 MHz. The 500-MHz bandwidth of the Ka-band altimeter on the Satellite with ARGOS and AltiKa mission should encounter these difficulties at smaller SWH values. Onboard range tracking and automatic gain control loops in future altimeters might be improved if zero-padding were employed during onboard waveform processing.

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

A novel digitally controlled automatic gain control (AGC) loop circuitry for the global navigation satellite system (GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier (PGA), an AGC circuit and an analog-to-digital converter (ADC), which is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from −4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.

A 2.2 mW, 40 dB Automatic Gain Controllable Low Noise Amplifier for FM Receiver

This paper presents an automatic gain controllable low noise amplifier (AGC-LNA) for FM receiver (FMRx). The proposed LNA adopts current reused dual g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -boosting technique for the power saving. And, a simple analog type automatic gain control (AGC) loop is proposed that provides high resolution gain control. Implemented in a 65 nm CMOS technology, measurements show power regulation range of 40 dB with ±1 dB error, less than -11 dB of S11, variable voltage gain range of -12 to 30 dB over the frequency range of 88 ~ 108 MHz, noise figure (NF) of less than 2.9 dB, P1dB of higher than -24.2 dBm, and IIP3 of higher than -12.7 dBm in the high gain (HG) mode, while dissipating only 1.8 mA from a 1.2 V supply, respectively.

A fully integrated feedback AGC loop for ZigBee (IEEE 802.15.4) RF transceiver applications

This work presents an efficient solution for automatic gain control (AGC) loop in ZigBee transceiver compatible to IEEE 802.15.4 standard. The design is based on a RF (Radio Frequency) and linear IF (Intermediate Frequency) chain where the signal amplification is done in the RF front-end blocks and analog VGAs (variable gain amplifiers). The gains of the RF block and VGA are digitally controlled by the DAGC (Digital AGC) block to ensure that the ADC (Analog-to-Digital Converter) operates inside its dynamic range. Feedback loop architecture is employed for the advantage of high linearity due to its inherent characteristic. The whole AGC loop has been integrated in the ZigBee transceiver which was fabricated in a 0.18μm CMOS technology. The AGC loop achieves a dynamic range of about 95dB with the gain error of less than ±0.5dB. The two-channel VGAs and peak detectors occupy an area of 1.5mm×0.4mm and dissipate 1.71mW from a single 1.8V power supply. The DAGC has been integrated in the digital baseband processor and occupies an area of about 0.4mm×0.4mm. The max gain lock time of the AGC loop is about 1.25μs.

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L1 and Compass-B1 in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control (AGC) loop is utilized to improve the receiver's robustness by optimizing the conversion gain of the analog-to-digital converter (ADC). While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure (NF) of about 1.8 dB, an image rejection (IMR) of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about −36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.

具有增益补偿功能的微机械陀螺数字化驱动闭环

A digital drive closed-loop method with gain compensation was proposed to improve the stability of scale factor for a micro-machined gyroscope.The working principle of the micro-machined gyroscope was analyzed and the analysis results on the dynamic equation show that in order to improve the stability of the scale factor,the stability of drive-mode vibration speed of the gyroscope should be improved.However,the stability of drive-mode vibration speed of the gyroscope is dependent on the stability of gain of a C/V conversion circuit in the drive closed-loop.Therefore,again compensation algorithm was proposed and the digital drive closed-loop with gain compensation was designed by combining with a automatic gain control loop and a phase locked loop.Simulation results show when the gain of C/V conversion circuit changes 7.4%in relative,the amplitude of vibration velocity changes from 7.29% without gain compensation to 0.12% with gain compensation.Experiment results indicate that the temperature coefficient of scale factor within-40℃to 60℃is reduced by 90%after gain compensation.It verifies that the digital drive closed-loop with gain compensation can significantly improve the stability of scale factor for the micro-machined gyroscope.

A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with an integrated automatic gain control (AGC) loop for a short-distance receiver are implemented in SMIC 0.13 μm CMOS technology. The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within ±0.5 dB for an input power from −65 to −8 dBm. The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA (I and Q paths) from a 1.2 V supply. Auto LNA gain mode selection with a combined RSSI function is also presented. Furthermore, with the compensation circuit, the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.

First CFOA-based explicit-current-output quadrature sinusoidal oscillators using grounded capacitors

To date, no current-feedback operational amplifier (CFOA)-based sinusoidal oscillator has been reported which provides all the following features simultaneously: (i) current-mode quadrature sinusoidal oscillator providing two explicit-current-outputs (ECOs) from high output impedance terminals, (ii) employing no more than three CFOA ICs and six passive components, which include two grounded capacitors, (iii) offers independent tuning of the condition of oscillation (CO) via a resistor and (iv) provides tunability of the ratio of amplitudes of the generated quadrature ECOs via a separate resistor. To the best of authors' knowledge, this article reports first CFOA-based QOs in current-mode (i.e. providing two ECO signals). Experimental results using AD844 CFOA ICs from Analog Devices have been included to verify the workability of the proposed oscillator circuits. An example automatic gain control (AGC) loop to regulate the oscillation amplitude and control the THD has also been used and verified using SPICE simulations using the AD844 macro-model.

A CMOS linear-in-dB VGA and AGC loop for telecommunication applications

In this paper, an Automatic Gain Control (AGC) loop which is based on a linear-in-dB Variable Gain Amplifier (VGA) is proposed. The VGA structure is based on simple nMOS differential pairs with variable tail currents. The linear-in-dB gain tuning schema is designed using a novel exponential current generator which also offers temperature compensation of the VGA's gain. The gain of the VGA is tuned by a control voltage with gain range about 28dB with ±1dB linearity error. The worst cases of the VGA gain, over process and temperature corners, are ±1.54dB and ±2.45dB for maximum and minimum gain setting, respectively. The proposed implementation is designed in a CMOS 90nm triple-well process with 1.2V supply voltage.

Reconfigurable Dual-Channel Multiband RF Receiver for GPS/Galileo/BD-2 Systems

A fully integrated dual-channel multiband RF receiver is designed and implemented for next-generation global navigation satellite systems (GNSSs) in a 0.18-μm CMOS process. Its two reconfigurable signal channels can simultaneously process any two types of 2-, 4-, or 20-MHz bandwidth signals mainly located around the RF bands of 1.2 and 1.57 GHz for GPS, Galileo, and BD-2 (aka Compass) systems, while achieving better performance (die area, noise figure, gain dynamic range) than other state-of-the-art GNSS receivers. A digital automatic gain control loop consisting of a variable gain amplifier and nonuniform 4-bit ADC is utilized to improve the receiver's robustness and performance in the presence of interferences. While drawing 25-mA current per channel from a 1.8-V supply, this RF receiver achieves a total noise figure of 2.5 dB/2.7 dB at 1.2/1.57 GHz, an image rejection of 28 dB, a maximum voltage gain of 110 dB, a gain dynamic range of 73 dB, and an input-referred 1-dB compression point of -58 dBm, with an active die area of 2.4 mm2 for single channel.

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

A 2-mW 50-dB DR wideband hybrid AGC for a GNSS receiver in 65 nm CMOS

A low-power wideband hybrid automatic gain control (AGC) loop for a GNSS receiver is presented. Single AGC in the I/Q path is composed of four-stage programmable gain amplifiers (PGAs), a differential peak detector, two comparators, a control algorithm logic, a decoder and the reference voltage source. Besides being controlled by an AGC loop, the gain of PGAs could alternatively be controlled by an off-chip digital baseband processor through the SPI interface. To obtain low power consumption and noise, an improved source degenerated amplifier is adopted, and the I/Q path phase mismatch within the ±5° range is calibrated with 0.2° accuracy. Implemented in 65 nm CMOS, the measured PGA total gains range from 9.8 to 59.5 dB with an average step of 0.95 dB and simulated bandwidth of more than 110 MHz. The settling time is about 180 μs with 80% AM input with measured signal power from −76.7 to −56.6 dBm from a radio-frequency amplifier (RFA) input port, and also reduces to 90 μs with clock frequency doubling. The single AGC consumes almost 0.8 mA current from the 2.5-V supply and occupies an area of 750 × 300 μm2.